Specifications

S1C62N82 TECHNICAL HARDWARE EPSON I-25
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
Table 4.2.1 lists the control bits and their addresses for the
oscillation circuit.
Table 4.2.1 Control bits of oscillation circuit and prescaler
Control of oscillation
circuit
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0FCH
CLKCHG OSCC 0 IOC CLKCHG
OSCC
0
IOC
0
0
0
CPU clock switch
OSC3 oscillator ON/OFF
I/O port P00–P03 Input/Output
OSC3
ON
Output
OSC1
OFF
Input
R/WR/W R
OSC3 oscillation control (0FCH D2)
Controls oscillation ON/OFF for the OSC3 oscillation circuit.
(S1C62A82 only.)
When 1 is written: The OSC3 oscillation ON
When 0 is written: The OSC3 oscillation OFF
Read-out: Valid
When it is necessary to operate the CPU of the S1C62A82 at
high speed, set OSCC to 1. At other times, set it to 0 to
lessen the current consumption.
For the S1C62N82 and 62L82, keep OSCC set to 0.
At initial reset, OSCC is set to 0.
The CPU's clock switch (0FCH D3)
The CPU's operation clock is selected with this register.
(S1C62A82 only.)
When 1 is written: OSC3 clock is selected
When 0 is written: OSC1 clock is selected
Read-out: Valid
When the S1C62A82's CPU clock is to be OSC3, set
CLKCHG to 1; for OSC1, set CLKCHG to 0. This register
cannot be controlled for the S1C62N82 and 62L82, so that
OSC1 is selected no matter what the set value.
At initial reset, CLKCHG is set to 0.
OSCC
CLKCHG