Specifications

S1C62N82 TECHNICAL HARDWARE EPSON I-23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

OSC3 oscillation

circuit

Fig. 4.2.3

OSC3 oscillation circuit

In the S1C62N82 Series, the S1C62A82 has twin clock

specification. The mask option enables selection of either

the CR or ceramic oscillation circuit (OSC3 oscillation cir-

cuit) as the CPU's subclock. Because the oscillation circuit

itself is built-in, it provides the resistance as an external

element when CR oscillation is selected, but when ceramic

oscillation is selected both the ceramic oscillator and two

capacitors (gate and drain capacitance) are required.

Figure 4.2.3 is the block diagram of the OSC3 oscillation

circuit.

As indicated in Figure 4.2.3, the CR oscillation circuit can

be configured simply by connecting the resistor (RCR) be-

tween terminals OSC3 and OSC4 when CR oscillation is

selected. When 35 k is used for R CR, the oscillation fre-

quency is about 1 MHz. When ceramic oscillation is se-

lected, the ceramic oscillation circuit can be configured by

connecting the ceramic oscillator (Typ. 1 MHz) between

terminals OSC3 and OSC4 to the two capacitors (CGC and

CDC) located between terminals OSC3 and OSC4 and VDD.

For both CGC and CDC, connect capacitors that are about

100 pF. To lower current consumption of the OSC3 oscilla-

tion circuit, oscillation can be stopped through the software.

For the S1C62N82 and 62L82 (single clock specification), do

not connect anything to terminals OSC3 and OSC4.

To CPU

Oscillation circuit

control signal

S1C62A82

OSC3