Specifications

II-80 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
This register enables or masks the 32 Hz timer interrupt.
The CPU is interrupted if it is in the EI state when the
interrupt mask register (EIT32) is set to "1" and the inter-
rupt condition flag (IT32) is "1". (See Figure 3.12.3.)
This register enables or masks the 8 Hz timer interrupt. The
CPU is interrupted if it is in the EI state when the interrupt
mask register (EIT8) is set to "1" and the interrupt condition
flag (IT8) is "1". (See Figure 3.12.3.)
This register enables or masks the 2 Hz timer interrupt. The
CPU is intterrupted if it is in the EI state when the interrupt
mask register (EIT2) is set to "1" and the interrupt condition
flag (IT2) is "1". (See Figure 3.12.3.)
This register enables or masks the 1 Hz stopwatch interrupt.
The CPU is interrupted if it is in the EI state when the
interrupt mask register (EISW1) is set to "1", and also the
interrupt condition flag (ISW1) is "1". (See Figure 3.12.4.)
This register enables or masks the 10 Hz stopwatch inter-
rupt. The CPU is interrupted if it is in the EI state when the
interrupt mask register (EISW0) is set to "1", and the inter-
rupt condition flag (ISW0) is "1". (See Figure 3.12.4.)
Write to the interrupt mask registers (EIT32, EIT8, EIT2) in DI
states only (interrupt flag [I] = "0").
EISW1
EIT2
EIT8
Note
EISW0
EIT32