Specifications

II-78 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
• Interrupt mask registers
The interrupt mask registers are registers that individually
specify whether to enable or mask the timer interrupt (2 Hz,
8 Hz, 32 Hz), stopwatch timer interrupt (1 Hz, 10 Hz), or
input interrupt (K00–K03, K10).
The following are descriptions of the interrupt mask regis-
ters.
This register enables or masks the K00–K03 input interrupt.
The interrupt condition flag (IK0) is set to "1" when the
contents of the input (K00–K03) and the interrupt differen-
tial register (KCP00–KCP03) do not match and the data of
the corresponding interrupt mask register (EIK00–EIK03) is
"1". The CPU is interrupted if it is in the EI state (interrupt
flag [I] = "1"). (See Figure 3.12.1.)
This register enables or masks the K10 input interrupt. The
interrupt condition flag (IK1) is set to "1" when the contents
of the input (K10) and the interrupt differential register
(KCP10) do not match and the data of the corresponding
interrupt mask register (EIK10) is "1". The CPU is inter-
rupted if it is in the EI state (interrupt flag [I] = "0"). (See
Figure 3.12.2.)
EIK00 to EIK03
EIK10
<Input interrupt programing related precautions>
When the content of the mask register is rewritten, while the port K
input is in the active status. The input interrupt factor flags are set at
➀ and ➁, ➀ being the interrupt due to the falling edge and ➁ the
interrupt due to the rising edge.
Fig. 3.12.5
Input interrupt timing
Port K input
Factor flag set Not set ➁ Factor flag set
Input comparison
register
Mask register
Active status
Active status
Rising edge interrupt
➀
Falling edge interrupt