Specifications

II-48 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Control of the SVD
circuit
The SVD circuit will turn ON by writing "1" on the SVDON
register (address 0FAH, D0, R/W) and supply voltage detec-
tion will be performed. By writing "0" on the SVDON register,
the detection result is stored in the SVDDT register. How-
ever, in order to obtain a stable detection result, it is neces-
sary to turn the SVD circuit ON for at least 100 µs. Accord-
ingly, reading out the detection result from the SVDDT
register is performed through the following procedures:
➀ Set the SVDON register to "1".
➁ Provide at least 100 µs waiting time.
➂ Set the SVDON register to "0".
➃ Read-out from the SVDDT register.
Note, however, that when S1C62N82 is to be used with the
OSC1 system clock at fosc1 = 32.768 kHz, there is no need
for the waiting time stated in the above procedure ➁ since 1
instruction cycle will take longer than 100 µs. When system
clock change to OSC3, it must delay some instructions.
Because the power current consumption of the IC becomes
large when the SVD circuit is operated, turn the SVD circuit
OFF when not in use. The operation timing chart is shown
in Figure 3.9.1.
Label Mnemonic/Operand Comment
LD X,0FAH ;Sets the address of SVDON
OR MX,0001B ;Sets SVDON to "1"
AND MX,1110B ;Sets SVDON to "0"
LD A,MX ;Loads the detection result
;into the A register
Example of SVD
circuit control
program
(At fosc1 = 32.768 kHz)
Supply voltage
Criteria voltage
SVDON register
SVD circuit
SVDDT register
HLMOD register
100 µs or more
Fig. 3.9.1
Timing chart of supply
voltage detection operation
through the SVDON
register