Specifications

II-40 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
The S1C62N82 contains a timer with a basic oscillation of
32.768 kHz (typical). This timer is a 4-bit binary counter,
and the counter data can be read as necessary. The counter
data of the 16 Hz clock can be read by reading TM3 to TM0
(address 0E4H, D3 to D0). ("1" to "0" are set in TM3 to TM0,
corresponding to the high-low levels of the 2 Hz, 4 Hz, 8 Hz,
and 16 Hz 50 % duty waveform. See Figure 3.7.1.) The
timer can also interrupt the CPU on the falling edges of the
32 Hz, 8 Hz, and 2 Hz signals. For details, see Section 3.12,
"Interrupt and Halt".
Control of the timer
The timer is reset by setting "1" in TMRST (address 0F9H,
D2).
The 128 Hz to 2 Hz of the internal divider is initialized by resetting
the timer, and 128 Hz to 1 Hz of the internal divider is reset by
resetting the stopwatch timer.
The dividers of the timer and stopwatch timers are individ-
ual circuits, so resetting one circuit does not affect the
other.
Clock timer timing chart Frequency
Register
bit
Address
0E4H
D0 16 Hz
D1
D2
D3
8 Hz
4 Hz
2 Hz
Occurrence of
32 Hz interrupt request
Occurrence of
8 Hz interrupt request
Occurrence of
2 Hz interrupt request
Fig. 3.7.1
Output waveform of
timer and interrupt timing
Note