Specifications

II-32 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
The S1C62N82 contains 320 bits of display memory in
addresses 090H to 0DFH of the data memory. Each display
memory can be assigned to any 304 bits of the 320 bits for
the LCD driver (38 SEG × 8 COM) or 168 bits of the 320 bits
(42 SEG × 4 COM) by using a mask option. The remaining
16 bits or 152 bits of display memory are not connected to
the LCD driver, and are not output even when data is writ-
ten. The memory which is not assigned may be used as
general-purpose RAM. An LCD segment is on with "1" set in
the display memory, and off with "0" set in the display
memory.
The contents of the display memory is indefinite during initial reset
and until the display memory is initialized (i.e., through memory
clearing process from the CPU, etc.), the data of the memory and
the contents of LCD display will not match.
Perform display memory initialization through initializing processes.
• LCD drive control register (CSDC)
The LCD drive control register (CSDC: address 0FBH, D3)
can be set either for dynamic drive or for static drive. Set "0"
in CSDC for 1/8 duty or 1/4 duty (time-shared) dynamic
drive. Set "1" in CSDC and the same value in the display
memories corresponding to COM0 to COM7 for static drive.
Figure 3.6.2 is the static drive control of the LCD, and
Figure 3.6.3 is an example of the 7-segment LCD assign-
ment.
In Figure 3.6.2 segment option set for 4 commons (COM0–
COM3), segment can use from SEG0–SEG41. If option set
for 8 commons (COM0–COM7), then segment can use from
SEG0–SEG37 only.
Even in case 1/4 duty were selected, when SEG terminal is set to
static driving, set the same values on all the display memories
corresponding to COM0–COM7.
Control of the LCD
driver
Note
Note