Specifications

S1C62N82 TECHNICAL SOFTWARE EPSON II-3
CHAPTER 1: CONFIGURATION
1.3 Interrupt Vectors
When an interrupt request is received by the CPU, the CPU
initiates the following interrupt processing after completing
the instruction being executed.
(1)The address of the next instruction to be executed (the
value of the program counter) is saved on the stack
(RAM).
(2)The interrupt vector address corresponding to the inter-
rupt request is loaded into the program counter.
(3)The branch instruction written in the vector is executed
to branch to the software interrupt processing routine.
Steps 1 and 2 require 12 cycles of the CPU system clock.
The correspondence between interrupt requests and vectors
are shown in Table 1.3.1.
When multiple interrupts occur simultaneously, they are
executed in order of priority.
Note
Table 1.3.1
Interrupt requests and vectors
Vector Priority Interrupt Request
10AH
108H
106H
104H
102H
1
2
3
4
5
Melody interrupt
Input (K10) interrupt
Input (K00–K03) interrupt
Stopwatch timer interrupt
Clock timer interrupt