Specifications

S1C62N82 TECHNICAL HARDWARE EPSON I-113
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Tables 4.12.4 (a)–(c) shows the interrupt control bits and
their addresses.
Table 4.12.4 (a) Interrupt control bits (1)
Control of interrupt
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E5H
0E6H
0E7H
KCP03 KCP02 KCP01 KCP00
0 0 0 KCP10
00 0EIMEL
R
R
R/W
KCP03
KCP02
KCP01
KCP00
0
0
0
0
Input comparison register (K03)
Input comparison register (K02)
Input comparison register (K01)
Input comparison register (K00)
0
0
0
KCP10
0
0
0
0
EIMEL
0 Enable Mask
Input comparison register (K10)
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Interrupt mask register (melody)
Falling Rising
R/W
R/W
0E8H
EIK03 EIK02 EIK01 EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask