Specifications

I-112 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Interrupt vectors and
priorities
Note
Table 4.12.3
Interrupt vectors
and priorities
Note
When an interrupt request is input to the CPU, the CPU
begins interrupt processing. After the program being exe-
cuted is suspended, interrupt processing is executed in the
following order:
➀ The address data (value of the program counter) of the
program step to be executed next is saved on the stack
(RAM).
➁ The interrupt request causes the value of the interrupt
vector (page 1, 02H–0BH) to be loaded into the program
counter.
➂ The program at the specified address is executed (execu-
tion of interrupt processing routine).
Table 4.12.3 shows the correspondence of interrupt vectors
and priorities.
The processing in steps 1 and 2, above, takes 12 cycles of the
CPU system clock.
Vector Priority Interrupt Request
10AH 1 Melody interrupt
108H 2 Input (K10) interrupt
106H 3 Input (K00–K03) interrupt
104H 4 Stopwatch timer interrupt
102H 5 Clock timer interrupt
When multiple interrupts occur simultaneously, the interrupt vec-
tors with higher priority will be executed.