Specifications

S1C62N82 TECHNICAL HARDWARE EPSON I-111
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
The interrupt factor flags can be masked by the correspond-
ing interrupt mask registers. The interrupt mask registers
are read/write registers. They are enabled (interrupt en-
abled) when 1 is written to them, and masked (interrupt
disabled) when 0 is written to them. After an initial reset,
the interrupt mask register is set to 0.
Table 4.12.2 shows the correspondence between interrupt
mask registers and interrupt factor flags.
Interrupt Mask Register
EIT2 (0EBH D2)
EIT8 (0EBH D1)
EIT32 (0EBH D0)
EISW1 (0EAH D1)
EISW0 (0EAH D0)
EIK03 * (0E8H D3)
EIK02 * (0E8H D2)
EIK01 * (0E8H D1)
EIK00 * (0E8H D0)
EIK10 * (0E9H D0)
EIMEL (0E7H D0)
Interrupt Factor Flag
IT2 (0EFH D2)
IT8 (0EFH D1)
IT32 (0EFH D0)
ISW1 (0EEH D1)
ISW0 (0EEH D0)
IK0 (0EDH D0)
IK1 (0EDH D1)
IMEL (0ECH D0)
* There is an interrupt mask register for each input port pin.
Writing to the interrupt mask registers should be done only in the
DI status (interrupt flag = 0). Otherwise it causes malfunction.
Specific masks and
factor flags for inter-
rupt
Table 4.12.2
Interrupt mask registers and
interrupt factor flags
Note