Specifications

I-106 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
CLKC0
CLKC1
0
0
1
1
0
1
0
1
Normal
8 times
16 times
32 times
CLKC1 CLKC0 Playing Speed
Note
MAD0–MAD6
Playing Speed Control Register (0F2H D2)
Playing Speed Control Register (0F2H D3)
By operating these registers, playing speed of a melody may
be changed. The combination of CLKC0 and CLKC1 register
values and playing speed are shown in Table 4.11.10.
When 1 is written: 1
When 0 is written: 0
Reading: Valid
Playing speeds are changed the moment these registers are
operated. Take caution when operating these registers in the
middle of a melody playing.
Address Registers (0F0H D0–D3 and 0F1H D0–D2)
These registers are used to set the melody playing start. By
operating the "MELC" register, when playing of a new mel-
ody starts, the addresses set in these registers are read by
the melody ROM address counter and become the melody
start addresses.
When 1 is written: 1
When 0 is written: 0
Reading: Valid
Table 4.11.10
Playing speed