Specifications
I-70 EPSON S1C6S2N7 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Tables 4.11.4 (a) and (b) shows the interrupt control bits
and their addresses.
Control of interrupt
Table 4.11.4 (a) Interrupt control bits (1)
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0E8H
0EAH
0EBH
EIK03 EIK02 EIK01 EIK00
0 0 EISW1 EISW0
0 EIT2 EIT8 EIT32
R
R
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
0
0
EISW1
EISW0
0
0
0
EIT2
EIT8
EIT32
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Enable
Enable
Mask
Mask
*5
*5
R/W
*5
R/W
0E9H
0 0 0 EISMD
R
0
0
0
EISW0
0
Interrupt mask register (motor driver)
Enable Mask
*5
*5
*5
R/W
0EDH
00 IK0
R
0
0
0
IK0
0
Interrupt factor flag (K00–K03)
Yes No
*5
*5
*5
*4
0
0ECH
0 0 ISMD
R
0
0
0
ISMD
0
Interrupt factor flag (motor driver)
Yes No
*5
*5
*5
0