Specifications

I-68 EPSON S1C6S2N7 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
The interrupt factor flags can be masked by the correspond-
ing interrupt mask registers. The interrupt mask registers
are read/write registers. They are enabled (interrupt en-
abled) when 1 is written to them, and masked (interrupt
disabled) when 0 is written to them. After an initial reset,
the interrupt mask register is set to 0.
Table 4.11.2 shows the correspondence between interrupt
mask registers and interrupt factor flags.
Specific masks and
factor flags for inter-
rupt
Table 4.11.2
Interrupt mask registers and
interrupt factor flags
Interrupt Mask Register
EIT2
EIT8
EIT32
EISW1
EISW0
EIK03*
EIK02*
EIK01*
EIK00*
EISMD
Interrrupt Factor Flag
(0EBH D2)
(0EBH D1)
(0EBH D0)
(0EAH D1)
(0EAH D0)
(0E8H D3)
(0E8H D2)
(0E8H D1)
(0E8H D0)
(0E9H D0)
IT2
IT8
IT32
ISW1
ISW0
ISMD
(0EFH D2)
(0EFH D1)
(0EFH D0)
(0EEH D1)
(0EEH D0)
(0ECH D0)
IK0 (0EDH D0)
* There is an interrupt mask register for each input port pin.