Specifications

S1C6S2N7 TECHNICAL HARDWARE EPSON I-65
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Interrupt and HALT
The S1C6S2N7 Series provides the following interrupt set-
tings, each of which is maskable.
External interrupt: Input interrupt (one)
Internal interrupt: Timer interrupt (one)
Stopwatch interrupt (one)
Motor driver interrupt (one)
To enable interrupts, the interrupt flag must be set to 1 (EI)
and the necessary related interrupt mask registers must be
set to 1 (enable). When an interrupt occurs, the interrupt
flag is automatically reset to 0 (DI) and interrupts after that
are inhibited.
When a HALT instruction is input, the CPU operating clock
stops and the CPU enters the halt state. The CPU is reacti-
vated from the halt state when an interrupt request occurs.
Figure 4.11.1 shows the configuration of the interrupt
circuit.
4.11