Specifications

I-64 EPSON S1C6S2N7 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver)
ISMD Interrupt factor flag (0ECH D0)
This is the flag that indicates a motor driver interrupt.
When 1 is read: Interrupt has occurred
When 0 is read: Interrupt has not occurred
Writing: Invalid
The software can determine from this flag whether there is a
motor driver interrupt. However, this flag is set to 1 after a
motor drive sequence is finished even if the interrupt has
been masked.
This flag is reset when the software has read it.
Reading of interrupt factor flag is available at EI, but be
careful in the following cases.
If the interrupt mask register value corresponding to the
interrupt factor flag to be read is set to 1, an interrupt
request will be generated by the interrupt factor flag set
timing, or an interrupt request will not be generated.
After an initial reset, this flag is set to 0.
PF pulse drive status/trigger (0FEH D1)
This bit is used as the PF pulse drive trigger and as the drive
status indicator.
When 1 is written: PF pulse drive trigger
When 0 is written: No operation
When 1 is read: PF pulse drive status RUN state
When 0 is read: PF pulse drive status STOP state
Note that the function of this bit is different at reading and
writing.
When 1 is written to this bit, it functions as the PF pulse
drive trigger to start a pulse output. When this bit is read,
the read content indicates the PF pulse drive status.
After an initial reset, FRUN is set to 0.
FRUN, FTRG