Specifications

I-62 EPSON S1C6S2N7 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver)
Drive pulse
By writing 1 to the FTRG register (address 0FEH D1), the
stepping motor drive pulse PF can be output.
The PF pulse width is selectable in 0.244 msec steps within
the range of 1.46 msec to 7.08 msec. Thus it is possible to
rotate the hands of a watch in a maximum 78 Hz.
The A01 and A02 terminals output the drive pulse PF
alternately with every 1 written to the FTRG register. The
first drive pulse after system reset is output from the A01
terminal.
Fig. 4.10.2
Timing chart
The mask option for the motor driver enables selection of
the drive pulse (PF) width.
The drive pulse width can be selected in 0.244 msec steps
within the range of 1.464 msec to 7.076 msec.
The motor driver generates an interrupt when it has finished
a pulse output sequence.
An output sequence begins within 1 msec after 1 is written
to the FTRG register and takes 11.7 msec to end. When the
sequence has finished, the interrupt factor flag (ISMD) is set
to 1 and an interrupt occurs.
The interrupt can be masked by the interrupt mask register
(EISMD). However, the interrupt factor flag is set to 1 after
a sequence is finished regardless of the interrupt mask
register setting.
Write to the interrupt mask register (EISMD) only in the DI status
(interrupt flag = 0). Otherwise, it may cause malfunction.
Mask option
Interrupt function
Note
A01 or A02
FTRG
1.46 ms
7.08 ms
3.9 ms
PF
Max. 1.0 ms
11.7 ms (1 sequence)