Specifications

I-54 EPSON S1C6S2N7 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
SWRST Stopwatch timer reset (0F9H D0)
This bit resets the stopwatch timer.
When 1 is written: Stopwatch timer reset
When 0 is written: No operation
Reading: Always 0
The stopwatch timer is reset when 1 is written to SWRST.
When the stopwatch timer is reset while running, operation
restarts immediately. Also, while stopped, the reset data is
maintained.
This bit is write-only, and is always 0 when read.
SWRUN Stopwatch timer run/stop (0F9H D1)
This bit controls run/stop of the stopwatch timer.
When 1 is written: Run
When 0 is written: Stop
Reading: Valid
The stopwatch timer runs when 1 is written to SWRUN, and
stops when 0 is written.
When stopped, the timer data is maintained until the timer
next Run or is reset. Also, when the timer runs after being
stopped, the data that was maintained can be used to res-
ume the count.
If the timer data is read while running, a correct read may
be impossible because of the carry from the low-order bit
(SWL) to the high-order bit (SWH). This occurs if reading
has extended over the SWL and SWH bits when the carry
occurs. To prevent this, read after stopping, and then
continue running. Also, the stopped duration must be
within 976 µs (256 Hz, 1/4 cycle).
After an initial reset, this register is set to 0.