Specifications

S1C6S2N7 TECHNICAL HARDWARE EPSON I-9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Oscillation detection
circuit
The oscillation detection circuit outputs the initial reset
signal at power-on until the oscillation circuit starts
oscillating, or when the oscillation circuit stops oscillating
for some reason.
However, depending on the power-on sequence (voltage rise
timing), the circuit may not work properly. Therefore, use
the reset terminal or reset by simultaneous high input to the
input port (K00–K03) for initial reset after turning power on.
An initial reset can be invoked externally by making the
reset pin high. This high level must be maintained for at
least 5 ms (when the oscillation frequency fosc is 32 kHz),
because the initial reset circuit contains a noise rejection
circuit. When the reset pin goes low the CPU begins to
operate.
Another way of invoking an initial reset externally is to input
a high signal simultaneously to the input ports (K00–K03)
selected with the mask option. This initial reset signal
passes through the noise rejection circuit. Therefore, it is
necessary to keep the specified input ports at high level for
at least a definite time. This time can be selected from 4
sec, 2 sec, 62.5 msec and 250 msec (when the oscillation
frequency fosc is 32 kHz) by mask option. Tables 2.2.1 and
2.2.2 show the combinations of input ports (K00–K03) and
the simultaneous high input detection time that can be
selected with the mask option.
A Not used
B K00*K01
C K00*K01*K02
D K00*K01*K02*K03
1 2–4 [sec]
2 1–2 [sec]
3 30–62.5 [msec]
4 120–250 [msec]
Reset pin (RESET)
Simultaneous high
input to input ports
(K00–K03)
Table 2.2.1
Input port combinations
Table 2.2.2
Simultaneous high input
detection time