Specifications

II-60 EPSON S1C6S2N7 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
• Interrupt vector address
The S1C6S2N7 interrupt vector address is made up of the
low-order 4 bits of the program counter (12 bits), each of
which is assigned a specific function as shown in Figure
3.10.6.
0
PCP3
0
PCP2
0
PCP1
1
PCP0
0
PCS7
0
PCS6
0
PCS5
0
PCS4
×
PCS3
×
PCS2
×
PCS1
×
PCS0
Motor driver interrupt
Input (K00–K03) interrupt
Stopwatch interrupt
Clock timer interrupt
Note that all of the three timer interrupts have the same
vector address, and software must be used to judge whether
or not a given timer interrupt has occurred. For instance,
when the 32 Hz timer interrupt and the 8 Hz timer interrupt
are enabled at the same time, the accepted timer interrupt
must be identified by software. (Similarly, the K00–K03
input interrupts and the 10 Hz/1 Hz stopwatch interrupts
must be identified by software.)
When an interrupt is generated, the hardware resets the
interrupt flag (I) to enter the DI state. Execute the EI in-
struction as necessary to recover the EI state after interrupt
processing.
Set the EI state at the start of the interrupt processing
routine to allow nesting of the interrupts.
The interrupt factor flags must always be reset before set-
ting the EI status in the corresponding interrupt processing
routine. (The flag is reset when the interrupt factor flag is
read by software.)
If the EI instruction is executed without resetting the inter-
rupt factor flag after generating the timer interrupt or the
stopwatch timer interrupt, and if the corresponding inter-
rupt mask register is still "1", the same interrupt is gener-
ated once more. (See Figure 3.10.7.)
Fig. 3.10.6
Assignment of the interrupt
vector address