Specifications

II-58 EPSON S1C6S2N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)

• Interrupt mask registers

The interrupt mask registers are registers that individually

specify whether to enable or mask the motor driver

interrupt, timer interrupt (2 Hz, 8 Hz, 32 Hz), stopwatch

timer interrupt (1 Hz, 10 Hz), or input interrupt (K00–K03).

The following are descriptions of the interrupt mask regis-

ters.

EIK00 to EIK03 This register enables or masks the K00–K03 input interrupt.

The interrupt factor flag (IK0) is set to "1" when the contents

of the input (K00–K03) become "1" and the data of the

corresponding interrupt mask register (EIK00–EIK03) is "1".

The CPU is interrupted if it is in the EI state (interrupt flag

[I] = "1"). (See Figure 3.10.1.)

When using an input interrupt, if you rewrite the content of

the mask register, when the value of the input terminal

which becomes the interrupt input is in the active status

(input terminal = high status), the factor flag for input

interrupt may be set.

For example, a factor flag is set with the timing of ➀ shown

in Figure 3.10.5. However, when clearing the content of the

mask register with the input terminal kept in the high

status and then setting it, the factor flag of the input inter-

rupt is again set at the timing that has been set.

When the content of the mask register is rewritten, while

the port K input is in the active status. The input interrupt

factor flag is set at ➀.

Fig. 3.10.5

Input interrupt timing

Port K input

Factor flag set Not set

Mask register

Active status

➀