Specifications

II-50 EPSON S1C6S2N7 TECHNICAL SOFTWARE

CHAPTER 3: PERIPHERAL CIRCUITS (Motor Driver)

By writing 1 to the FTRG register (address 0FEH D1), the

motor drive pulse PF can be output.

The PF pulse width is selectable in 0.244 msec steps within

the range of 1.46 msec to 7.08 msec.

The A01 and A02 terminals output the drive pulse PF

alternately with every 1 written to the FTRG register. The

first drive pulse after system reset is output from the A01

terminal.

Control of the motor

driver

A01

FRUN

Interrupt generation

A02

3.9 ms

1.46–7.08 ms

FTRG

11.7 ms (1 sequence)

Max. 1.0 ms

• Drive pulse PF output from the A01 or A02 terminals

Label Mnemonic/operand Comment

LD X,0FEH ;Set address of the motor driver

;FTRG register

OR MX,0010B ;Set FTRG to "1"

The two instruction steps output the motor drive pulse PF

from the A01 or A02 terminals.

Examples of motor

driver control

program

Fig. 3.9.1

Timing chart