Specifications

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MF881

Technical Manual

CMOS 4

BIT SINGLE CHIP MICROCOMPUTER

S1C6S2N7 Technical Hardware/S1C6S2N7 Technical Software

S1C6S2N7

Summary of content (191 pages)

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MF881-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C6S2N7 Technical Manual S1C6S2N7 Technical Hardware/S1C6S2N7 Technical Software
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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
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PREFACE This part explains the function of the S1C6S2N7, the circuit configurations, and details the controlling method. II. S1C6S2N7 Technical Software This part explains the programming method of the S1C6S2N7. Software I. S1C6S2N7 Technical Hardware Hardware This manual is individualy described about the hardware and the software of the S1C6S2N7.
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The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
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Hardware I.
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CONTENTS CONTENTS CHAPTER 2 INTRODUCTION ............................................................... I-1 1.1 Configuration ................................................................... I-1 1.2 Features .......................................................................... I-2 1.3 Block Diagram ................................................................. I-3 1.4 Pin Layout Diagram ......................................................... I-4 1.5 Pin Description ................
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CONTENTS CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...................... I-13 4.1 Memory Map .................................................................. I-13 4.2 Oscillation Circuit ............................................................ I-19 Crystal oscillation circuit ......................................... I-19 CR oscillation circuit ............................................... I-19 4.3 Input Ports (K00–K03) ....................................................
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CONTENTS Stopwatch Timer ............................................................ I-49 Configuration of stopwatch timer ............................ Count-up pattern .................................................... Interrupt function ................................................... Control of stopwatch timer ...................................... 4.9 I-49 I-50 I-51 I-52 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function .............................
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CONTENTS CHAPTER 7 CHAPTER 8 I-iv 6.3 DC Characteristics ......................................................... I-77 6.4 Analog Circuit Characteristics and Current Consumption . I-79 6.5 Oscillation Characteristics .............................................. I-85 6.6 Motor Driver Characteristics ........................................... I-87 PACKAGE ...................................................................... I-88 7.1 Plastic Package ...........................................
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CHAPTER 1: INTRODUCTION CHAPTER 1 INTRODUCTION Each member of the S1C6S2N7 Series of single chip microcomputers features a 4-bit S1C6200A core CPU, 1,536 words of ROM (12 bits per word), 80 words of RAM (4 bits per word), an LCD driver, 4 bits for input ports (K00–K03), 4 bits for output ports (R00–R03), 4 bits for I/O ports (P00– P03), two timers (clock timer and stopwatch timer) and a motor driver.
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CHAPTER 1: INTRODUCTION 1.2 Features Built-in oscillation circuit Crystal or CR oscillation circuit, 32.768 kHz (typ.
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CHAPTER 1: INTRODUCTION ROM 1,536 × 12 RESET OSC1 OSC2 1.3 Block Diagram OSC System Reset Control Core CPU S1C6200A RAM 80 × 4 COM0 | COM3 SEG0 | SEG25 VDD VL1 | VL3 CA CB VS1 VSS (FOUT/BUZZER) (BUZZER) Interrupt Generator LCD Driver Power Controller Input Port Test Port K00–K03 I/O Port P00–P03 Output Port R00–R03 TEST Timer SVD Stop Watch Fout & Buzzer Motor Driver A01, A02 DT1, DT2 Fig. 1.3.
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CHAPTER 1: INTRODUCTION 1.4 Pin Layout Diagram QFP6-60pin 45 31 46 30 Index 60 16 1 Fig. 1.4.1 15 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 OSC1 16 COM2 2 OSC2 17 COM3 31 TEST 46 P01 32 SEG13 47 P02 3 N.C.
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CHAPTER 1: INTRODUCTION 1.5 Pin Description Table 1.5.1 Pin description Pin Name Pin No. Input/Output Function VDD 60 (I) Power source (+) pin VSS 59 (I) Power source (-) pin VS1 4 O Oscillation and internal logic system regulated voltage output pin VL1 7 O LCD system regulated voltage output pin (approx. -1.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (*1) supplied to VDD through VSS, the S1C6S2N7 Series generates the necessary internal voltages with the regulated voltage circuit ( for oscillators and internal circuit, for LCDs) and the voltage booster ( for LCDs). Figure 2.1.1 shows the power supply configuration of the S1C6S2N7. *1 Supply voltage: Note - S1C6S2N7 .... S1C6S2A7 ...
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET The LCD system regulated voltage circuit use can be prohibited by setting the mask option. In this case, external elements can be minimized because the external capacitors for the LCD system regulated voltage circuit are not necessary. However when the LCD system regulated voltage circuit is not used, the display quality of the LCD panel, when the supply voltage fluctuates (drops), is inferior to when the LCD system regulated voltage circuit is used.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C6S2N7 Series circuits, an initial reset must be executed. There are three ways of doing this. (1) Initial reset by the oscillation detection circuit (2) External initial reset via the RESET pin (3) External initial reset by simultaneous high input to pins K00–K03 (depending on mask option) Figure 2.2.1 shows the configuration of the initial reset circuit.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET Oscillation detection The oscillation detection circuit outputs the initial reset signal at power-on until the oscillation circuit starts circuit oscillating, or when the oscillation circuit stops oscillating for some reason. However, depending on the power-on sequence (voltage rise timing), the circuit may not work properly. Therefore, use the reset terminal or reset by simultaneous high input to the input port (K00–K03) for initial reset after turning power on.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET When, for instance, mask option D (K00*K01*K02*K03) is selected, an initial reset is executed when the signals input to the four ports K00–K03 are all high at the same time. If you use this function, make sure that the specified ports do not go high at the same time during normal operation. Internal register following initialization Table 2.2.3 Initial values An initial reset initializes the CPU as shown in the table below.
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CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C6S2N7 Series employs the S1C6200A core CPU, so that register configuration, instructions, and so forth are virtually identical to those in other processors in the family using the S1C6200A. Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200A. Note the following points with regard to the S1C6S2N7 Series: (1) The SLEEP operation is not provided, so the SLP instruction cannot be used.
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CHAPTER 3: CPU, ROM, RAM 3.2 ROM The built-in ROM, a mask ROM for the program, has a capacity of 1,536 × 12-bit steps. The program area is 6 pages (0–5), each consisting of 256 steps (00H–FFH). After an initial reset, the program start address is page 1, step 00H. The interrupt vector is allocated to page l, steps 01H– 0FH. Bank 0 00H step 0 page Program start address 01H step 1 page 2 page Interrupt vector area 3 page 4 page 5 page 0FH step 10H step Program area FFH step Fig. 3.2.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C6S2N7 Series are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.2 Oscillation Circuit Crystal oscillation circuit The S1C6S2N7 Series has a built-in crystal oscillation circuit. This circuit generates the operating clock for the CPU and peripheral circuit on connection to an external crystal oscillator (typ. 32.768 kHz) and trimmer capacitor (5–25 pF). Figure 4.2.1 is the block diagram of the crystal oscillation circuit. VDD CG RD To CPU and peripheral circuits Rf X'tal OSC1 VDD CD OSC2 Fig.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3 Input Ports (K00–K03) Configuration of input port The S1C6S2N7 Series has a 4-bit general-purpose input port. Each of the input port pins (K00–K03) has an internal pull-down resistance. The pull-down resistance can be selected for each bit with the mask option. Figure 4.3.1 shows the configuration of input port. Interrupt request Kxx Data bus VDD Address Fig. 4.3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Data bus Kxx Address Noise rejector Interrupt factor flag (IK0) Interrupt request Address Fig. 4.3.2 Input interrupt circuit configuration (K00–K03) Interrupt mask register (EIK) Mask option Address The interrupt mask registers (EIK00–EIK03) enable the interrupt mask to be selected individually for K00–K03. An interrupt occurs when the input value which are not masked change and the interrupt factor flag (IK0) is set to 1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Consequently, when the input terminal is in the active status (high status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (low status).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Control of input port Table 4.3.1 list the input port control bits and their addresses. Table 4.3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) EIK00–EIK03 Interrupt mask registers (0E8H) Masking the interrupt of the input port pins can be done with these registers. When 1 is written: Enable When 0 is written: Mask Reading: Valid With these registers, masking of the input port bits can be done for each of the four bits. After an initial reset, these registers are all set to 0. IK0 Interrupt factor flag (0EDH D0) This flag indicates the occurrence of an input interrupt.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.4 Output Ports (R00–R03) Configuration of output port The S1C6S2N7 Series has a 4-bit general output port (R00– R03). Output specification of the output port can be selected in a bit unit with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Also, the mask option enables the output ports R00 and R01 to be used as special output ports. Figure 4.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) The mask option enables the following output port selection. Mask option (1) Output specification of output port The output specifications for the output port (R00–R03) may be either complementary output or Pch open drain output for each of the four bits. However, even when Pch open drain output is selected, a voltage exceeding the source voltage must not be applied to the output port.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) FOUT (R00) When output port R00 is set for FOUT output, this port will generate fosc (CPU operating clock frequency) or clock frequency divided into fosc. Clock frequency may be selected individually for F1–F4, from among 5 types by mask option; one among F1–F4 is selected by software and used. The types of frequency which may be selected are shown in Table 4.4.2. Table 4.4.2 FOUT clock frequency Mask Option Sets Clock Frequency (Hz) fosc = 32.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Table 4.4.3 lists the output port control bits and their addresses. Control of output port Table 4.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00 (when FOUT is Special output port data (0F3H D0) selected) Controls the FOUT (clock) output. When 1 is written: When 0 is written: Reading: Clock output Low level (DC) output Valid FOUT output can be controlled by writing data to R00. After an initial reset, this register is set to 0. Figure 4.4.3 shows the output waveform for FOUT output. R00 register Fig. 4.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00, R01 (when BUZZER Special output port data (0F3H D0, 0F3H D1) and BUZZER is Controls the buzzer output. selected) When 1 is written: Buzzer output When 0 is written: Low level (DC) output Reading: Valid BUZZER and BUZZER output can be controlled by writing data to R00 and R01. When BUZZER output by R01 register control is selected by mask option, BUZZER output and BUZZER output can be controlled simultaneously by writing data to R01 register.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.5 I/O Ports (P00–P03) The S1C6S2N7 Series has a 4-bit general-purpose I/O port. Figure 4.5.1 shows the configuration of the I/O port. The four bits of the I/O port P00–P03 can be set to either input mode or output mode. The mode can be set by writing data to the I/O control register (IOC). Data bus Configuration of I/O port Input control Register Pxx Address Fig. 4.5.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Input or output mode can be set for the four bits of I/O port P00–P03 by writing data into I/O control register IOC. To set the input mode, 0 is written to the I/O control register. When an I/O port is set to input mode, its impedance becomes high and it works as an input port. However, the input line is pulled down when input data is read. I/O control register and I/O mode The output mode is set when 1 is written to the I/O control register (IOC).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) P00–P03 I/O port data (0F6H) I/O port data can be read and output data can be written through the port. • When writing data When 1 is written: When 0 is written: High level Low level When an I/O port is set to the output mode, the written data is output from the I/O port pin unchanged. When 1 is written as the port data, the port pin goes high (VDD), and when 0 is written, the level goes low (VSS). Port data can also be written in the input mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) IOC I/O control register (0FCH D0) The input or output I/O port mode can be set with this register. When 1 is written: When 0 is written: Reading: Output mode Input mode Valid The input or output mode of the I/O port is set in units of four bits. For instance, IOC sets the mode for P00–P03. Writing 1 to the I/O control register makes the I/O port enter the output mode, and writing 0, the input mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6 LCD Driver (COM0–COM3, SEG0–SEG25) Configuration of LCD The S1C6S2N7 Series has four common pins and 26 (SEG0– SEG25) segment pins, so that an LCD with a maximum of driver 104 (26 × 4) segments can be driven. The power for driving the LCD is generated by the CPU internal circuit, so there is no need to supply power externally.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 -VDD -VL1 -VL2 -VL3 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0–25 COM2 Not lit Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0–25 Fig. 4.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 -VDD -VL1 -VL2 -VL3 LCD lighting status COM0 COM1 COM2 COM1 SEG0–25 COM2 Not lit Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0–25 Fig. 4.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1 -VL2 -VL3 COM0 LCD lighting status COM0 COM1 SEG0–25 COM1 Not lit COM2 Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0–25 Fig. 4.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0–25 COM2 Not lit COM3 Lit -VDD -VL1, L2 -VL3 SEG 0–25 Fig. 4.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0–25 COM2 Not lit COM3 Lit -VDD -VL1, L2 -VL3 SEG 0–25 Fig. 4.6.5 Drive waveform for Frame frequency 1/3 duty (1/2 bias) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 SEG0–25 COM2 Not lit COM3 Lit -VDD -VL1, L2 -VL3 SEG 0–25 Fig. 4.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Switching between dynamic and static drive The S1C6S2N7 Series allows software setting of the LCD static drive. This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the OSC circuit. The procedure for executing of the LCD static drive is as follows: ➀ Write 1 to the CSDC register at address 0FBH D3. ➁ Write the same value to all registers corresponding to COMs 0 through 3 of the display memory.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (1) Segment allocation Mask option (segment allocation) As shown in Figure 4.l.1, the S1C6S2N7 Series display data is decided by the display data written to the display memory (write-only) at address 090H–0AFH. The address and bits of the display memory can be made to correspond to the segment pins (SEG0–SEG25) in any combination through mask option.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (2) Drive duty According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty. Table 4.6.1 shows the differences in the number of segments according to the selected duty. Table 4.6.1 Differences according to selected duty Note Duty Pins Used in Common Maximum Number of Segments Frame Frequency (when fosc = 32 kHz) 1/4 1/3 1/2 COM0–3 COM0–2 COM0–1 104 (26 × 4) 78 (26 × 3) 52 (26 × 2) 32 Hz 42.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Table 4.6.2 shows the control bits of the LCD driver and their addresses. Figure 4.6.9 shows the display memory map. Control of LCD driver Table 4.6.2 Control bits of LCD driver Address Register D2 D1 D3 CSDC 0 Name SR 1 0 0 CSDC 0 Static Dynamic 0 R R/W Comment D0 LCD drive switch 0 0FBH 0 0 Address Fig. 4.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.7 Clock Timer Configuration of clock timer The S1C6S2N7 Series has a built-in clock timer driven by the source oscillator. The clock timer is configured as a seven-bit binary counter that serves as a frequency divider taking a 256 Hz source clock from the oscillation circuit. The four high-order bits (16 Hz–2 Hz) can be read by the software.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Interrupt function Address 0E4H The clock timer can interrupt on the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. The software can mask any of these interrupt signals. Figure 4.7.2 is the timing chart of the clock timer. Register Frequency bits D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz Clock timer timing chart Occurrence of 32 Hz interrupt request Occurrence of 8 Hz interrupt request Occurrence of 2 Hz interrupt request Fig. 4.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Table 4.7.1 shows the clock timer control bits and their addresses. Control of clock timer Table 4.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0–D2) These registers are used to mask the clock timer interrupt. When 1 is written: Enabled When 0 is written: Masked Reading: Valid The interrupt mask register bits (EIT32, EIT8, EIT2) mask the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz). After an initial reset, these registers are all set to 0.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.8 Stopwatch Timer Configuration of stopwatch timer The S1C6S2N7 Series incorporates a 1/100 sec and 1/10 sec stopwatch timer. The stopwatch timer is configured as a two-stage, four-bit BCD timer serving as the clock source for an approximately 100 Hz signal (obtained by approximately dividing the 256 Hz source clock from the oscillation circuit). Data can be read out four bits at a time by the software. When CR oscillator (typ.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) Count-up pattern The stopwatch timer is configured as two four-bit BCD timers, SWL and SWH. The SWL timer, at the stage preceding the stopwatch timer, has an approximate l00 Hz signal as its input clock. It counts up every 1/100 sec and generates an approximate 10 Hz signal. The SWH timer has an approximate 10 Hz signal generated by the SWL timer for its input clock. It counts up every 1/10 sec and generates a 1 Hz signal. Figure 4.8.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be generated by the overflow of the SWL and SWH stopwatch timers, respectively. Also, software can separately mask the frequencies as described earlier. Figure 4.8.3 is the timing chart for the stopwatch timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) Control of stopwatch Table 4.8.1 shows the stopwatch timer control bits and their addresses. timer Table 4.8.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) SWL0–SWL3 1/100 sec stopwatch timer (0E2H) Data (BCD) of the 1/100 sec column of the stopwatch timer can be read. These four bits are read-only, and cannot be written to. After an initial reset, the timer data is set to 0H. SWH0–SWH3 1/10 sec stopwatch timer (0E3H) Data (BCD) of the 1/10 sec column of the stopwatch timer can be read. These four bits are read-only, and cannot be written to. After an initial reset, the timer data is set to 0H.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) SWRST Stopwatch timer reset (0F9H D0) This bit resets the stopwatch timer. When 1 is written: Stopwatch timer reset When 0 is written: No operation Reading: Always 0 The stopwatch timer is reset when 1 is written to SWRST. When the stopwatch timer is reset while running, operation restarts immediately. Also, while stopped, the reset data is maintained. This bit is write-only, and is always 0 when read.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) 4.9 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function Configuration of SVD circuit and heavy load protection function The S1C6S2N7 Series has a built-in supply voltage detection (SVD) circuit and a heavy load protection function. Figure 4.9.1 shows the configuration of the circuit.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) In the heavy load protection mode, the internally regulated voltage is generated by the liquid crystal driver source output VL2 so as to operate the internal circuit. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) Operation of SVD detection timing The following explains the timing when the SVD circuit writes the result of supply voltage detection to the SVDDT register. The result of supply voltage detection is written to the SVDDT register by the SVD circuit, and this data can be read by the software to determine the supply voltage. There are two methods, explained below, for executing the detection by the SVD circuit.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) Operation of heavy load protection function The S1C6S2N7 Series has a heavy load protection function for when the battery load becomes heavy and the supply voltage drops, such as when a melody is played or an external lamp lights. This functions works in the heavy load protection mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) Table 4.9.1 shows the control bits and their addresses for the SVD circuit and the heavy load protection function. Control of SVD circuit and heavy load protection function Table 4.9.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function) SVDON SVD control on/off (0FAH D0) When 0 is written: SVD detection off When 1 is written: SVD detection on Reading: Valid When this bit is written, the SVD detection on/off operation is controlled. Large current is drawn during SVD detection, so keep SVD detection off except when necessary. When SVDON is set to 1, SVD detection is executed.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver) 4.10 Stepping Motor Driver Configuration of motor driver The S1C6S2N7 Series has a built-in stepping motor driver that is suitable for combination watches with low power consumption. Figure 4.10.1 shows the configuration of the motor driver.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver) By writing 1 to the FTRG register (address 0FEH D1), the stepping motor drive pulse PF can be output. The PF pulse width is selectable in 0.244 msec steps within the range of 1.46 msec to 7.08 msec. Thus it is possible to rotate the hands of a watch in a maximum 78 Hz. The A01 and A02 terminals output the drive pulse PF alternately with every 1 written to the FTRG register.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver) Table 4.10.1 shows the motor driver control bits and their addresses. Control of motor driver Table 4.10.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver) ISMD Interrupt factor flag (0ECH D0) This is the flag that indicates a motor driver interrupt. When 1 is read: When 0 is read: Writing: Interrupt has occurred Interrupt has not occurred Invalid The software can determine from this flag whether there is a motor driver interrupt. However, this flag is set to 1 after a motor drive sequence is finished even if the interrupt has been masked. This flag is reset when the software has read it.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.11 Interrupt and HALT The S1C6S2N7 Series provides the following interrupt settings, each of which is maskable. External interrupt: Internal interrupt: Input interrupt (one) Timer interrupt (one) Stopwatch interrupt (one) Motor driver interrupt (one) To enable interrupts, the interrupt flag must be set to 1 (EI) and the necessary related interrupt mask registers must be set to 1 (enable).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Interrupt vector (MSB) ISMD : Program counter of CPU (four low-order bits) EISMD : K00 (LSB) EIK00 K01 INT (Interrupt request) EIK01 IK0 K02 Interrupt flag EIK02 K03 EIK03 ISW0 EISW0 ISW1 EISW1 IT2 Interrupt factor flag EIT2 Interrupt mask register IT8 EIT8 IT32 EIT32 Fig. 4.11.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.11.1 shows the factors that generate interrupt requests. Interrupt factors The interrupt factor flags are set to 1 depending on the corresponding interrupt factors. The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to 1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Specific masks and factor flags for interrupt Table 4.11.2 Interrupt mask registers and interrupt factor flags The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt enabled) when 1 is written to them, and masked (interrupt disabled) when 0 is written to them. After an initial reset, the interrupt mask register is set to 0.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is suspended, interrupt processing is executed in the following order: Interrupt vectors ➀ The address data (value of the program counter) of the program step to be executed next is saved on the stack (RAM).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Tables 4.11.4 (a) and (b) shows the interrupt control bits and their addresses. Control of interrupt Table 4.11.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.11.
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CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM (1) Piezo Buzzer Single Terminal Driving COM3 I COM0 K00 SEG25 SEG0 LCD PANEL CA CB C1 Connection depending on power supply and LCD panel specification. Please refer to pages I-6 and I-7. VL1 K03 VL2 VL3 P00 I/O VDD CG P03 A01 Stepping Motor O S1C6S2N7/6S2A7 6S2B7/6S2L7 OSC1 X'tal RCR OSC2 VS1 A02 RESET R00 TEST C5 1.5 V or 3.
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CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM (2) Piezo Buzzer Direct Driving COM3 I COM0 K00 SEG25 SEG0 LCD PANEL CA CB C1 Connection depending on power supply and LCD panel specification. Please refer to pages I-6 and I-7. VL1 K03 VL2 VL3 P00 I/O VDD CG P03 A01 Stepping Motor X'tal RCR OSC2 VS1 A02 RESET R00 TEST C5 1.5 V or 3.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating S1C6S2N7/S1C6S2A7 (VDD=0V) Item Symbol Rated Value Unit Supply voltage Input voltage (1) Input voltage (2) Operating temperature Storage temperature Soldering temperature / time Allowable dissipation *1 VSS VI VIOSC Topr Tstg Tsol PD -5.0 to 0.5 VSS-0.3 to 0.5 VSS-0.3 to 0.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.2 Recommended Operating Conditions S1C6S2N7 (Ta=-20 to 70°C) Item Supply voltage Oscillation frequency Booster capacitor Between VDD and VL1 or VSS and VL1 Between VDD and VL2 or VSS and VL2 Capacitor between VDD and VL3 Capacitor between VDD and VS1 Symbol VSS fOSC fOSC C1 C2 C3 C4 C5 Condition VDD=0V Crystal oscillation CR oscillation, R=470kΩ Min. Typ. Max. Unit -3.6 -3.0 32.768 65 -2.2 V kHz kHz µF µF µF µF µF 80 0.1 0.1 0.1 0.1 0.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C6SL27 Item Supply voltage (Ta=-20 to 70°C) Symbol VSS Condition VDD=0V ∗3 VDD=0V With software control ∗1 Oscillation frequency Booster capacitor Capacitor between VDD and VL1 Capacitor between VDD and VL2 Capacitor between VDD and VL3 Capacitor between VDD and VS1 fOSC C1 C2 C3 C4 C5 Min. Typ. Max. Unit -1.8 -1.8 -1.5 -1.5 -1.1 -0.9 ∗2 V V 32.768 kHz µF µF µF µF µF 0.1 0.1 0.1 0.1 0.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.3 DC Characteristics S1C6S2N7/S1C6S2A7/S1C6S2B7 Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C6SL27 Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.4 Analog Circuit Characteristics and Current Consumption S1C6S2N7 (Crystal oscillation, Normal operating mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C6S2L7 (Crystal oscillation, Normal operating mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 µF Item Internal voltage Symbol VL1 VL2 VL3 SVD voltage SVD circuit response time Current consumption Condition Min. Typ. Max.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C6S2B7 (Crystal oscillation, Normal operating mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 µF Item Internal voltage Symbol VL1 VL2 VL3 SVD voltage SVD circuit response time Current consumption Condition Min. Typ. Max.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C6S2N7 (CR oscillation, Normal operating mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 µF, Recommended external resistance for CR oscillation=470 kΩ Item Internal voltage Symbol VL1 VL2 VL3 SVD voltage SVD circuit response time Current consumption Condition Min.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C6S2A7 (CR oscillation, Normal operating mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=200 kHz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C6S2B7 (CR oscillation, Normal operating mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 µF, Recommended external resistance for CR oscillation=470 kΩ Item Internal voltage Symbol VL1 VL2 VL3 SVD voltage SVD circuit response time Current consumption Condition Min. Typ. Max.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.5 Oscillation Characteristics Oscillation characteristics will vary according to different conditions. Use the following characteristics are as reference values. S1C6S2N7 Unless otherwise specified VDD=0 V, VSS=-3.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C6S2N7 (CR oscillation) Unless otherwise specified VDD=0 V, VSS=-3.0 V, RCR=470 kΩ, Ta=25°C Item Symbol Oscillation frequency dispersion Oscillation start voltage Oscillation start time Oscillation stop voltage fosc Vsta tsta Vstp Condition Min. Typ. Max. Unit -20 -2.2 65kHz 20 % V ms V VSS=-2.2 to -3.6V 3 -2.2 S1C6S2A7 (CR oscillation) Unless otherwise specified VDD=0 V, VSS=-3.
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CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.6 Motor Driver Characteristics Unless otherwise specified VDD=0 V, VSS=-1.58 V, Crystal: Q13MC146, CG=25 pF, CD=built-in, Ta=25°C Item Output voltage Diode characteristic Output driver leak (Pch) S1C6S2N7 TECHNICAL HARDWARE Symbol Vout ID Ileak Condition VSS=-1.35V RL=2kΩ Vn=0.6V EPSON Min. Typ. Max. Unit 1 V µA MΩ 1.
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CHAPTER 7: PACKAGE CHAPTER 7 PACKAGE 7.1 Plastic Package QFP6-60pin 17.6 14.0 ±0.4 ±0.2 45 31 17.6 14.0 ±0.4 30 ±0.2 46 Index 60 16 1 15 ±0.15 2.7 ±0.1 0.35 0.15 ±0.05 0.8 0~10° 0.85 ±0.2 1.
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CHAPTER 7: PACKAGE 7.2 Ceramic Package for Test Samples QFP6-60pin 17.00 13.97 ±0.3 ±0.15 45 31 17.00 ±0.15 13.97 ±0.3 30 46 Index 16 60 1 15 0.35 ±0.1 3.32 0.15 ±0.05 ±0.1 0.80 ±0.1 0~12° 0.70 ±0.1 1.515 ±0.
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CHAPTER 8: PAD LAYOUT CHAPTER 8 PAD LAYOUT 8.1 Diagram of Pad Layout 10 15 5 1 55 Y 20 (0, 0) X 50 25 Die No.
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CHAPTER 8: PAD LAYOUT 8.2 Pad Coordinates Pad No. Pad Name X Y Pad No.
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Software II.
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CONTENTS CONTENTS CHAPTER 2 CHAPTER 3 CONFIGURATION ........................................................... II-1 1.1 S1C6S2N7 Block Diagram ............................................. II-1 1.2 ROM Map ....................................................................... II-2 1.3 Interrupt Vectors ............................................................. II-3 1.4 Data Memory Map .......................................................... II-4 INITIAL RESET .............................
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CONTENTS 3.4 I/O Ports ........................................................................ II-24 I/O port memory map ............................................. II-24 Control of the I/O port ............................................ II-25 Examples of I/O port control program ..................... II-26 3.5 LCD Driver ..................................................................... II-29 LCD driver memory map ......................................... II-29 Control of the LCD driver .......
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CONTENTS SUMMARY OF PROGRAMMING POINTS....................... II-66 APPENDIX A Table of Instructions ...................................................... II-70 B The S1C6S2N7 I/O Memory Map ................................. II-75 C Table of the ICE Commands ......................................... II-77 D Cross-assembler Pseudo-instruction List ......................
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CHAPTER 1: CONFIGURATION CHAPTER 1 CONFIGURATION ROM 1,536 × 12 RESET OSC1 OSC2 1.1 S1C6S2N7 Block Diagram OSC System Reset Control Core CPU S1C6200A RAM 80 × 4 COM0 | COM3 SEG0 | SEG25 VDD VL1 | VL3 CA CB VS1 VSS (FOUT/BUZZER) (BUZZER) Interrupt Generator LCD Driver Power Controller Input Port Test Port K00–K03 I/O Port P00–P03 Output Port R00–R03 TEST Timer SVD Stop Watch Fout & Buzzer Motor Driver A01, A02 DT1, DT2 Fig. 1.1.
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CHAPTER 1: CONFIGURATION 1.2 ROM Map The S1C6S2N7 has a built-in mask ROM with a capacity of 1,536 steps × 12 bits for program storage. The configuration of the ROM is shown in Figure 1.2.1. Bank 0 00H step 0 page Program start address 01H step 1 page 2 page Interrupt vector area 3 page 4 page 5 page 0FH step 10H step Program area FFH step Fig. 1.2.
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CHAPTER 1: CONFIGURATION 1.3 Interrupt Vectors When an interrupt request is received by the CPU, the CPU initiates the following interrupt processing after completing the instruction being executed. (1) The address of the next instruction to be executed (the value of the program counter) is saved on the stack (RAM). (2) The interrupt vector address corresponding to the interrupt request is loaded into the program counter.
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CHAPTER 1: CONFIGURATION 1.4 Data Memory Map The S1C6S2N7 built-in RAM has 80 words of data memory, 32 words of display memory for the LCD, and I/O memory for controlling the peripheral circuit. When writing programs, note the following: (1) Since the stack area is in the data memory area, take care not to overwrite the stack with data. Subroutine calls or interrupts use 3 words on the stack. (2) Data memory addresses 000H–00FH are memory register areas that are addressed with register pointer RP.
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CHAPTER 1: CONFIGURATION Table 1.4.
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CHAPTER 1: CONFIGURATION Table 1.4.
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CHAPTER 1: CONFIGURATION Table 1.4.
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CHAPTER 1: CONFIGURATION Table 1.4.
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CHAPTER 1: CONFIGURATION Table 1.4.
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CHAPTER 2: INITIAL RESET CHAPTER 2 INITIAL RESET 2.1 Internal Register Status on Initial Reset Following an initial reset, the internal registers and internal data memory area are initialized to the values shown in Tables 2.1.1 and 2.1.2. Table 2.1.1 Initial values of internal registers Table 2.1.
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CHAPTER 2: INITIAL RESET After an initial reset, the program counter page (PCP) is initialized to 1H, and the program counter step (PCS), to 00H. This is why the program is executed from step 00H of the first page. The initial values of some internal registers and internal data memory area locations are undefined after a reset. Set them as necessary to the proper initial values in the program. The peripheral I/O functions (memory-mapped I/O) are assigned to internal data memory area addresses 0E0H to 0FEH.
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CHAPTER 2: INITIAL RESET 2.2 Initialize Program Example The following is a program that clears the RAM and LCD, resets the flags, registers, timer, and stopwatch timer, and sets the stack pointer immediately after resetting the system.
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CHAPTER 2: INITIAL RESET ; LD LD LD LD RST EI X,0 Y,0 A,0 B,0 F,0 ; ; ; Reset register flags ; ; ;Enable interrupt The above program is a basic initialization program for the S1C6S2N7. The setting data are all initialized as shown in Table 2.1.1 by executing this program. When using this program, add setting items necessary for each specific application. (Figure 2.2.1 is the flow chart for this program.
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CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports) CHAPTER 3 PERIPHERAL CIRCUITS Details on how to control the S1C6S2N7 peripheral circuit is given in this chapter. 3.1 Input Ports Input port memory map Table 3.1.
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CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports) The S1C6S2N7 has one 4-bit input port (K00–K03). Input port data can be read as a 4-bit unit (K00–K03). Control of the input port The state of the input ports can be obtained by reading the data (bits D3, D2, D1, D0) of address 0E0H. The input ports can be used to send an interrupt request to the CPU via the input interrupt condition flag. See Section 3.10 "Interrupt and Halt", for details.
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CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports) • Bit-unit checking of input ports Label Mnemonic/operand DI LD INPUT1: FAN JP INPUT2: FAN JP Y,0E0H MY,0010B NZ,INPUT1 MY,0010B Z,INPUT2 Comment ;Disable interrupt ;Set address of port ; ;Loop until K01 becomes "0" ; ;Loop until K01 becomes "1" This program loopes until a rising edge is input to input port K01. The input port can be addressed using the X register instead of the Y register.
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CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports) 3.2 Output Ports Output port memory map Table 3.2.
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CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports) Examples of output port control program • Loading B register data into R00–R03 Label Mnemonic/operand Comment LD LD ;Set address of port ;R00–R03 ← B register Y,0F3H MY,B As shown in Figure 3.2.1, the two instruction steps above load the data of the B register into the output ports. B register D3 D2 Fig. 3.2.
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CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports) • Bit-unit operation of output ports Label Mnemonic/operand Comment LD OR AND ;Set address of port ;Set R01 to 1 ;Set R02 to 0 Y,0F3H MY,0010B MY,1011B The three instruction steps above cause the output port to be set, as shown in Figure 3.2.2. Address 0F3H D3 R03 D2 R02 D1 R01 D0 R00 No change Sets "1" Sets "0" No change Fig. 3.2.
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CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) 3.3 Special Use Output Ports Special use output port memory map Table 3.3.
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CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) In addition to the regular DC, special output can be selected for output ports R00 and R01, as shown in Table 3.3.2. Figure 3.3.1 shows the structure of output ports R00–R03. Control of the special use output port Table 3.3.
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CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) Examples of special use output port control program • Buzzer driver output (BUZZER) When output port R01 is set for BUZZER and R00 is set for BUZZER, it performs 2,048 Hz or 4,096 Hz selected by register XBZR (0FDH D3).
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CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) • Internal divided frequency output (FOUT) When output port R00 is set to FOUT output, fosc or clock frequency divided into fosc is generated. Clock frequency may be selected individually for F1–F4, from among 5 types by mask option; a clock frequency is then selected from 4 types (i.e., F1–F4) through XFOUT0 and XFOUT1 (0FDH D0 and D1) registers and is generated. The clock frequency types are shown in Table 3.3.3. Table 3.3.
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CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) 3.4 I/O Ports I/O port memory map Table 3.4.
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CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) Control of the I/O port The S1C6S2N7 contains a 4-bit general I/O port (4 bits × 1). This port can be used as an input port or an output port, according to I/O port control register IOC. When IOC is "0", the port is set for input, when it is "1", the port is set for output. • How to set an input port Set "0" in the I/O port control register (D0 of address 0FCH), and the I/O port is set as an input port.
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CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) Examples of I/O port • Loading P00–P03 input data into A register control program Label Mnemonic/operand Comment LD AND LD LD ;Set address of I/O control port ;Set port as input port ;Set address of port ;A register ← P00–P03 Y,0FCH MY,1110B Y,0F6H A,MY As shown in Figure 3.4.1, the four instruction steps above load the data of the I/O ports into the A register. Fig. 3.4.
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CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) • Loading P00–P03 output data into A register Label Mnemonic/operand Comment LD Y,0FCH OR LD LD MY,0001B Y,0F6H A,MY ;Set the address of input/output ;port control register ;Set as output port ;Set the address of port ;A register ← P00–P03 As shown in Figure 3.4.2, the four instruction steps above load the data of the I/O ports into the A register. A register D3 D2 D1 D0 P03 P02 P01 P00 Fig. 3.4.
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CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) • Loading contents of B register into P00–P03 Label Mnemonic/operand Comment LD Y,0FCH OR LD LD MY,0001B Y,0F6H MY,B ;Set the address of input/output ;port control register ;Set port as output port ;Set the address of port ;P00–P03 ← B register As shown in Figure 3.4.3, the four instruction steps above load the data of the B register into the I/O ports. B register D3 D2 Fig. 3.4.
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CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) 3.5 LCD Driver LCD driver memory map Table 3.5.
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CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) Control of the LCD driver The S1C6S2N7 contains 128 bits of display memory in addresses 090H to 0AFH of the data memory. Each display memory can be assigned to any 104 bits of the 128 bits for the LCD driver (26 SEG × 4 COM) or 78 bits of the 128 bits (26 SEG × 3 COM) by using a mask option. The remaining 24 bits or 50 bits of display memory are not connected to the LCD driver, and are not output even when data is written.
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CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) LCD lighting status -VDD -VL1 -VL2 -VL3 COM 0–3 COM0 COM1 COM2 COM3 Frame frequency SEG0–25 -VDD -VL1 -VL2 -VL3 Not lit Lit SEG 0–25 -VDD -VL1 -VL2 -VL3 Fig. 3.5.2 1/1 duty drive control (1/3 bias) a f b g Address 090H e Fig. 3.5.3 7-segment LCD assignment c 091H Register D3 D2 D1 D0 d c g b f a e d In the assignment shown in Figure 3.5.
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CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) Examples of LCD driver control program • Displaying 7-segment The LCD display routine using the assignment of Figure 3.5.3 can be programmed as follows.
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CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) • Bit-unit operation of the display memory Address Fig. 3.5.
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CHAPTER 3: PERIPHERAL CIRCUITS (Timer) 3.6 Timer Timer memory map Table 3.6.
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CHAPTER 3: PERIPHERAL CIRCUITS (Timer) Control of the timer Address 0E4H Register bit Frequency D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz The S1C6S2N7 contains a timer with a basic oscillation of 32.768 kHz (typical). This timer is a 4-bit binary counter, and the counter data can be read as necessary. The counter data of the 16 Hz clock can be read by reading TM3 to TM0 (address 0E4H, D3 to D0).
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CHAPTER 3: PERIPHERAL CIRCUITS (Timer) Examples of timer control program • Initializing the timer Label Mnemonic/operand Comment LD Y,0F9H OR MY,0100B ;Set address of the timer ;reset register ;Reset the timer The two instruction steps above are used to reset (clear TM0–TM3 to 0) and restart the timer. The TMRST register is cleared to "0" by hardware 1 clock after it is set to "1".
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CHAPTER 3: PERIPHERAL CIRCUITS (Timer) • Checking timer edge Label Mnemonic/operand Comment LD CP X,TMSTAT MX,0 JP LD LD Z,RETURN Y,0E4H A,MY LD XOR Y,TMDTBF MY,A FAN LD MX,0100B MY,A JP ADD Z,RETURN MX,0FH ;Set address of the timer edge counter ;Check whether the timer edge ;counter is "0" ;Jump if "0" (Z-flag is "1") ;Set address of the timer ;Read the data of TM0 to TM3 ;into A register ;Set address of the timer data buffer ;Did the count on the timer ;change? ;Check bit D2 of the timer dat
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CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer) 3.7 Stopwatch Timer Stopwatch timer memory map Table 3.7.
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CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer) Control of the stopwatch timer The S1C6S2N7 contains 1/100 sec and 1/10 sec stopwatch timers. This timer can be loaded in 4-bit units. Starting, stopping, and resetting the timer can be controlled by register. Figure 3.7.1 shows the operation of the stopwatch timer.
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CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer) Examples of stopwatch timer control program • Initializing the stopwatch timer Label Mnemonic/operand Comment LD OR ;Set address of the SWRST register ;Reset the stopwatch timer Y,0F9H MY,0001B The two instruction steps above reset the stopwatch timer. (SWL3 to SWL0, SWH3 to SWH0 are all cleared to "0".) Note The stopwatch timer is reset by setting "1" in the SWRST register.
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CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer) • Loading the stopwatch timer Label Mnemonic/operand Comment LD Y,0E2H LDPY A,MY LD B,MY ;Set address of the SWL of ;the stopwatch ;Read the data of SWL0 to SWL3 ;into A register ;Read the data of SWH0 to SWH3 ;into B register The three instruction steps above reads the contents of the stopwatch timer into A register and B register. (Also see Table 3.7.2.) Table 3.7.
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) 3.8 Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function The S1C6S2N7 Series has a built-in supply voltage detection circuit and drop in supply voltage may be detected by controlling the register on the I/O memory. Criteria voltages are as follows: Model Criteria Voltage S1C6S2N7/S1C6S2A7 S1C6S2L7/S1C6S2B7 2.4 V ± 0.15 V 1.2 V ± 0.
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Control of the SVD circuit The SVD circuit will turn ON by writing "1" on the SVDON register (address 0FAH, D0, R/W) and supply voltage detection will be performed. By writing "0" on the SVDON register, the detection result is stored in the SVDDT register. However, in order to obtain a stable detection result, it is necessary to turn the SVD circuit ON for at least 100 µs.
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Heavy load protection function Note that the heavy load protection function on the S1C6S2L7/S1C6S2B7 are different from the S1C6S2N7/ S1C6S2A7. (1) In case of S1C6S2L7/S1C6S2B7 The S1C6S2L7/S1C6S2B7 have the heavy load protection function for when the battery load becomes heavy and the source voltage drops, such as when an external buzzer sounds or an external lamp lights.
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) The normal mode changes to the heavy load protection mode in the following case: • When the software changes the mode to the heavy load protection mode (HLMOD = "1") The heavy load protection mode switches the constant voltage circuit of the LCD system to the high-stability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode.
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Examples of heavy load protection function control program • Operation through the HLMOD register This is a sample program when lamp is driven with the R00 terminal during performance of heavy load protection.
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) • Operation through the SVDON register Label Mnemonic/operand Comment LD FAN JP OR AND FAN JP X,0FAH MX,1010B NZ,HLMOD MX,0001B MX,1110B A,0010B Z,HLMOD ;Sets the HLMOD/SVDDT address ;Checks the HLMOD/SVDDT bits ;Heavy load protection mode ;Sets the SVDON to "1" ;Sets the SVDON to "0" ;Checks the SVDDT bit ;Shifts the mode to ;the heavy load protection mode LD AND RET Y,FLAG MY,0 ;Resets the flag to "0" Y,FLAG MY,1 ;S
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CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Start HLMOD? =1 =0 SVDDT? =1 =0 SVDON←1 SVDON←0 SVDDT? =1 =0 FLAG←0 FLAG←1 Fig. 3.8.
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CHAPTER 3: PERIPHERAL CIRCUITS (Motor Driver) 3.9 Motor Driver Motor driver memory map Table 3.9.
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CHAPTER 3: PERIPHERAL CIRCUITS (Motor Driver) Control of the motor driver By writing 1 to the FTRG register (address 0FEH D1), the motor drive pulse PF can be output. The PF pulse width is selectable in 0.244 msec steps within the range of 1.46 msec to 7.08 msec. The A01 and A02 terminals output the drive pulse PF alternately with every 1 written to the FTRG register. The first drive pulse after system reset is output from the A01 terminal. 11.7 ms (1 sequence) Max. 1.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) 3.10 Interrupt and Halt Interrupt memory map Table 3.10.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Table 3.10.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Control of interrupts and halt The S1C6S2N7 supports four types of a total of 10 interrupts. There are one motor driver interrupt, three timer interrupts (2 Hz, 8 Hz, 32 Hz), two stopwatch interrupts (1 Hz, 10 Hz) and four input interrupts (K00–K03). The 10 interrupts are individually enabled or masked (disabled) by interrupt mask registers.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) • Interrupt factor flags IK0 This flag is set when any of the K00 to K03 input interrupts occurs. The interrupt factor flag (IK0) is set to "1" when the contents of the input (K00–K03) become "1" and the data of the corresponding interrupt mask register (EIK00–EIK03) is "1". The contents of the IK0 flag can be loaded by software to determine whether the K00–K03 input interrupts have occured. The flag is reset when loaded by software. (See Figure 3.10.1.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) IT32 This flag is set to "1" when a falling edge is detected in the timer TM1 (32 Hz) signal. The contents of the IT32 flag can be loaded by software to determine whether a 32 Hz timer interrupt has occured. The flag is reset, when it is loaded by software. (See Figure 3.10.2.) IT8 This flag is set to "1" when a falling edge is detected in the timer TM1 (8 Hz) signal.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) ISW1 This flag is set to "1" when a falling edge is detected in the stopwatch timer (SWH, 1 Hz). The contents of the ISW1 flag can be loaded by software to determine whether a 1 Hz stopwatch interrupt has occured. The flag is reset, when it is loaded by software. (See Figure 3.10.3.) ISW0 This flag is set to "1" when a falling edge is detected in the stopwatch timer (SWH, 10 Hz).
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) ISMD This flag is set to "1" after a motor drive sequence is finished. The contents of the ISMD flag can be loaded by software to determine whether a motor drive interrupt has occured. Motor driver interrupt factor flag (ISMD) Data bus Motor driver The flag is reset, when it is loaded by software. (See Figure 3.10.4.) D0 Data bus Motor driver interrupt mask register (EISMD) INT (Interrupt request) D0 Fig. 3.10.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) • Interrupt mask registers The interrupt mask registers are registers that individually specify whether to enable or mask the motor driver interrupt, timer interrupt (2 Hz, 8 Hz, 32 Hz), stopwatch timer interrupt (1 Hz, 10 Hz), or input interrupt (K00–K03). The following are descriptions of the interrupt mask registers. EIK00 to EIK03 This register enables or masks the K00–K03 input interrupt.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Consequently, when the input terminal is in the active status (high status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (low status). EIT32 This register enables or masks the 32 Hz timer interrupt.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) • Interrupt vector address The S1C6S2N7 interrupt vector address is made up of the low-order 4 bits of the program counter (12 bits), each of which is assigned a specific function as shown in Figure 3.10.6. PCP3 PCP2 PCP1 PCP0 PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 0 0 0 1 0 0 0 0 × × × × Motor driver interrupt Fig. 3.10.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) If the EI state is set without resetting the interrupt factor flag after generating the input interrupt (K00–K03), the same interrupt is generated once more. (See Figure 3.10.7.) The interrupt factor flag must always be read (reset) in the DI state (interrupt flag [I] = "0"). There may be an operation error if read in the EI state.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Interrupt vector (MSB) ISMD : Program counter of CPU (four low-order bits) EISMD : K00 (LSB) EIK00 K01 INT (Interrupt request) EIK01 IK0 K02 Interrupt flag EIK02 K03 EIK03 ISW0 EISW0 ISW1 EISW1 IT2 Interrupt factor flag EIT2 Interrupt mask register IT8 EIT8 IT32 EIT32 Fig. 3.10.
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Examples of interrupt • Restart from halt state by interrupt and halt control Main routine program Label Mnemonic/operand Comment LD X,0E9H OR MX,0001B ;Set address of motor driver ;interrupt mask register ;Enable motor driver ;input interrupt LD X,0E8H OR MX,1111B LD X,0EAH OR MX,0011B LD X,0EBH OR MX,0111B EI HALT JP MAIN ; ;Set address of K00 to K03 ;interrupt mask register ;Enable K00 to K03 ;input interrupt ; ;Set address of st
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Interruption vector routine Label ; INTR: Mnemonic/operand Comment ORG JP JP JP JP JP JP JP JP JP JP JP JP JP JP JP JP 100H INIT INTR SW1RQ INTR IK0RQ INTR SW1RQ INTR IMDRQ INTR SW1RQ INTR IK0RQ INTR SW1RQ INTR ;Timer interrupt (TINT) is generated ;Stopwatch interrupt (SWINT) is generated ;TINT, SWINT are generated ;K00 to K03 input interrupt (KINT) is generated ;TINT, KINT are generated ;SWINT, KINT are generated ;TINT, SWINT, KINT are generated ;M
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CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) SW10RQ: LD Y,SWFSK FAN JP CALL ;Address of stopwatch interrupt ;factor flag buffer MY,0010B ;Check 10 Hz stopwatch interrupt Z,IK0RQ ;Jump if not 10 Hz stopwatch interrupt SW10IN ;Call 10 Hz stopwatch interrupt service routine LD FAN JP CALL X,0EDH MX,0001B Z,IMDRQ IK0INT ;Address of K00 to K03 input interrupt flag ;Check K00 to K03 input interrupt ;Jump if not K00 to K03 input interrupt ;Call K00 to K03 input interrupt service routine LD FAN JP CA
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CHAPTER 4: SUMMARY OF PROGRAMMING POINTS CHAPTER 4 SUMMARY OF PROGRAMMING POINTS • Core CPU After the system reset, only the program counter (PC), new page pointer (NPP) and interrupt flag (I) are initialized by the hardware. The other internal circuits whose settings are undefined must be initialized with the program. • Power Supply External load driving through the output voltage of constant voltage circuit or voltage booster is not permitted.
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CHAPTER 4: SUMMARY OF PROGRAMMING POINTS • Input Port – When modifying the input port from high level to low level with pull-down resistance, a delay will occur at the rise of the waveform due to time constant of the pulldown resistance and input gate capacities. Provide appropriate waiting time in the program when performing input port reading. – Input interrupt programing related precautions Port K input Active status Mask register ➀ Fig. 4.
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CHAPTER 4: SUMMARY OF PROGRAMMING POINTS • I/O Port – When the I/O port is set to the output mode and a lowimpedance load is connected to the port pin, the data written to the register may differ from the data read. – When the I/O port is set to the input mode and a lowlevel voltage (VSS) is input by the built-in pull-down resistance, an erroneous input results if the time constant of the capacitive load of the input line and the builtin pull-down resistance load is greater than the read-out time.
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CHAPTER 4: SUMMARY OF PROGRAMMING POINTS • Interrupt – Re-start from the HALT state is performed by the interrupt. The return address after completion of the interrupt processing in this case will be the address following the HALT instruction. – When interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI state. After completion of the interrupt processing, set to the EI state through the software as needed.
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APPENDIX A TABLE OF INSTRUCTIONS APPENDIX Classification Mnemonic A Table of Instructions Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation p 1 1 1 0 0 1 0 p4 p3 p2 p1 p0 5 NBP ← p4, NPP ← p3~p0 s 0 0 0 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB ← NBP, PCP ← NPP, PCS ← s7~s0 C, s 0 0 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB ← NBP, PCP ← NPP, PCS ← s7~s0 if C=1 NC, s 0 0 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB ← NBP, PCP ← NPP, PCS ← s7~s0 if C=0 Z, s 0 1 1 0 s7 s6 s5 s4 s3 s2 s1
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APPENDIX A TABLE OF INSTRUCTIONS Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation XH, i 1 0 1 0 0 1 0 0 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 XH-i3~i0 operation XL, i 1 0 1 0 0 1 0 1 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 XL-i3~i0 instructions YH, i 1 0 1 0 0 1 1 0 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 YH-i3~i0 YL, i 1 0 1 0 0 1 1 1 i3 i2 i1 i0 ↑ ↓ ↓ ↑ 7 YL-i3~i0 r, i 1 1 1 0 0 0 r1 r0 i3 i2 i1 i0 5 r ← i3~i0 transfer r, q 1 1 1 0 1 1 0 0 r1 r0 q1 q0 5 r ←q instructi
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APPENDIX A TABLE OF INSTRUCTIONS Classification Mnemonic Operation Code Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation YH 1 1 1 1 1 1 0 1 1 0 0 0 5 YH← M(SP), SP ← SP+1 operation YL 1 1 1 1 1 1 0 1 1 0 0 1 5 YL ← M(SP), SP ← SP+1 instructions F ↑ ↑ 1 1 1 1 1 1 0 1 1 0 1 0 ↓ ↑ ↓ ↓ ↑ ↓ 5 F ← M(SP), SP ← SP+1 SPH, r 1 1 1 1 1 1 1 0 0 0 r1 r0 5 SPH ← r SPL, r 1 1 1 1 1 1 1 1 0 0 r1 r0 5 SPL ← r r, SPH 1 1 1 1 1 1 1 0 0 1 r1 r0 5 r ← SPH r, SPL 1 1 1 1 1 1 1 1 0 1 r1
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APPENDIX A TABLE OF INSTRUCTIONS Abbreviations used in the explanations have the following meanings. Symbols associated with A .............. A register registers and memory B .............. B register X .............. XHL register (low order eight bits of index register IX) Y .............. YHL register (low order eight bits of index register IY) XH ........... XH register (high order four bits of XHL register) XL ............ XL register (low order four bits of XHL register) YH ............
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APPENDIX A TABLE OF INSTRUCTIONS Symbols associated with NBP ..... program counter NPP ..... PCB ..... PCP ..... PCS ..... PCSH .. PCSL ... New bank pointer New page pointer Program counter bank Program counter page Program counter step Four high order bits of PCS Four low order bits of PCS Symbols associated with F ......... Flag register (I, D, Z, C) flags C ......... Carry flag Z ......... Zero flag D ......... Decimal flag I .......... Interrupt flag ↓ ............. Flag reset ↑ .............
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APPENDIX B THE S1C6S2N7 I/O MEMORY MAP APPENDIX ADDRESS E0 E2 E3 E4 E8 E9 EA EB EC ED EE EF B The S1C6S2N7 I/O Memory Map DATA D3 K03 R D2 K02 R D1 K01 R D0 K00 R SWL3 R SWL2 R SWL1 R SWL0 R SWH3 R SWH2 R SWH1 R SWH0 R TM3 R TM2 R TM1 R TM0 R EIK03 R/W EIK02 R/W EIK01 R/W EIK00 R/W 0 R 0 R 0 R EISMD R/W 0 R 0 R EISW1 R/W EISW0 R/W 0 R EIT2 R/W EIT8 R/W EIT32 R/W 0 R 0 R 0 R ISMD R 0 R 0 R 0 R IK0 R 0 R 0 R ISW1 R ISW0 R 0 R IT2 R IT8 R S1C6S2N7
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APPENDIX B THE S1C6S2N7 I/O MEMORY MAP ADDRESS F3 F6 F9 FA FB FC DATA D3 R03 D2 R02 R/W D1 R01 BUZZER R/W D0 R00 FOUT R/W R/W P03 R/W P02 R/W P01 R/W P00 R/W 0 R TMRST W SWRUN R/W SWRST W HLMOD R/W 0 R SVDDT R SVDON R/W CSDC R/W 0 R 0 R 0 R 0 R 0 R 0 R IOC R/W XBZR R/W 0 R XFOUT1 R/W XFOUT0 R/W FD F3 II-76 0 0 R R FRUN FTRG R W 0 R NAME R03 R02 R01 BUZZER R00 FOUT P03 P02 P01 P00 0 TMRST SWRUN SWRST HLMOD 0 SVDDT SVDON CSDC 0 0 0 0 0 0 IOC XBZR 0 XFOUT1 XFOUT0
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APPENDIX C TABLE OF THE ICE COMMANDS APPENDIX Item No.
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APPENDIX C TABLE OF THE ICE COMMANDS Item No.
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APPENDIX D CROSS-ASSEMBLER PSEUDO-INSTRUCTION LIST APPENDIX D Cross-assembler Pseudo-instruction List Item No.
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S1C6S2N7 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.