Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-87
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Figure 4.12.12 shows the circuit diagram of the dual slope type A/
D converter built into S1C62740.
Operation of the
dual slope type A/D
converter
Fig. 4.12.12
Circuit diagram of A/D converter
This A/D converter performs A/D conversion according to the
following three sequences.
• Auto zero adjustment period
• Input integration period
• Reference voltage reverse integration period
The respective periods become as shown in Table 4.12.3 when
software (setting of register ADRS1 and ADRS0) is used to set the
resolution and conversion time.
Table 4.12.3
Conversion time
Auto zero Input Reverse Total
adjustment integration integration time
0 0 6,552 counts 200 msec 100 msec 200 msec 500 msec
0 1 3,276 counts 100 msec 50 msec 100 msec 250 msec
1 0 1,638 counts 50 msec 25 msec 50 msec 125 msec
1 1 820 counts 25 msec 12.5 msec 25 msec 62.5 msec
ADRS1 ADRS0 Resolution
Here below is provided an explanation of the operations in the
respective period. Refer to Figure 4.12.13 for the output waveforms
of each operational amplifier.
+
–
BUF
-VR
VR
V
IN
GND
+
–
+
–
CAZ CIBF
INT
CMP
GND
S
1
RI
S
2
S3
CO
To A/D converter
control circuit