Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX

I-86 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
As shown in Figure 4.12.10, it outputs an middle electric potential
(GND) through the operational amplifier buffer that divides the
source voltage impressed between V
DDA–VSSA into 1/2 by means of
a resistance. This GND becomes the reference potential of the A/D
converter.
Middle electric
potential (GND)
generation circuit
Fig. 4.12.10
Middle electric potential (GND)
generation circuit configuration
VSS/VSSA
VDD/VDDA
GND
+
3.3 µF
3.3 µF
+
–
+
The load drive by GND generated on the inside, presumes a load
connection between GND and V
SS.
When connecting a load between V
DD and GND, it is necessary to
change over the driving capacity through the software. This
changeover is done as shown in Table 4.12.2 by registers GNDON1
and GNDON0. When a large driving capacity has been set using
this function, the current consumption of the operational amplifier
also increases to beyond the current consumption of the load, so
you should be careful of this.
When the load becomes large, you should externally impress the
middle electric potential as shown in Figure 4.12.11. In this case
set the built-in middle electric potential generation circuit to OFF
using the GNDON1 and GNDON0 registers.
V
SS
/V
SSA
V
DD
/V
DDA
GND
+
+
3.3 µF
3.3 µF
Fig. 4.12.11
External impression of middle
electric potential
Table 4.12.2
Control of the middle electric
potential generation circuit
Refer to Chapter 7, "ELECTRICAL CHARACTERISTICS", for the
specific values of the load driving capacities.
GNDON1 GNDON0 Middle electric potential generation circuit
0 0 OFF (external impression)
0 1 ON (V
DD side load driving capacity – small)
1 0 ON (V
DD side load driving capacity – medium)
1 1 ON (V
DD side load driving capacity – large)