Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-85
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Fig. 4.12.9
External impression of VR1
Fig. 4.12.8
External adjustment
for VR1 andVR2
(4) External impression on VR1
When a high precision voltage from a built-in reference voltage is
necessary, you can impress an external voltage onto the V
R1
terminal. In this case, select the external adjustment mode by the
mask option.
You should set the voltage to be impressed on the V
R1 terminal so
that the result of measurement error of the A/D converter becomes
a minimum value.
The voltage on the V
SS side (negative) serves as the GND reference.
When impressed from the outside, it is necessary to set the register
VRON to "0" and to turn the built-in reference voltage generation
circuit OFF. After an initial reset, the VRON is set to "0".
V
R1
V
RA
V
R2
GND
0.1 µF
10 kΩ
VRON = "0"
VRAON = "0"
19 kΩ
(≈ -163.8 mV)
(≈ -475.0 mV)
V
R1
V
RA
V
R2
GND
VRON = "1"
VRAON = "0"
19 kΩ
(≈ -475.0 mV)
20 kΩ
15 kΩ
~1.5 MΩ
0.1 µF
10 kΩ
(≈ -163.8 mV)
+
–
GND
(5) VR and -VR generation circuit
This circuit generates a reference voltage that is output to the A/D
converter for the reverse integration period (described hereafter).
At the time of voltage measurement and differential voltage meas-
urement, V
R2 is output by this circuit as the reference voltage. At
the time of resistance measurement it outputs V
R1 the voltage
obtained by the external attached resistance.
Since an analog input voltage and a reverse polarity reference
voltage is necessary for A/D conversion, it accordingly creates the
reference voltages of both polarities, VR and -VR.