Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-82 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Since the input voltage of each terminal is limited to a maximum of
±320 mV, when measuring voltage that is likely to exceed this
range, you should input a voltage that has been voltage divided to
less than ±320 mV.
AIx
GND
GND
R1
R2
V
AI
V
IN
V
IN
=
R2
R1 + R2
V
AI
Fig. 4.12.4
Attenuator circuit when it exceeds
±320 mV
(2) Differential voltage measurement
• Measurement terminal: AI0–AI1 and AI2–AI3
• Input voltage: Max. ±420 mV (GND reference)
• Voltage between terminals: Max. ±320 mV
In this mode, the A/D converter measures the voltage input be-
tween the terminals AI0 and AI1 or between the terminals AI2 and
AI3. The AI0 or AI2 voltage levels are respectively input as the
reference voltage of the integral AMP. As a result, the difference
between the voltage level based on AI0 or AI2 and the voltage level
of AI1 or AI3 is measured. The voltage between the terminals AI0
and AI1 and between the terminals AI2 and AI3 are limited to a
maximum of ±320 mV. However, even when the voltage between
terminals is less than ±320 mV, the voltage level based on the GND
is limited to less than ±420 mV with any terminal.
AI0(AI2)
To non inverted input
of integral AMP
S
2
(S
3
)
AI1(AI3)
+
–
BUF
VR, -VR
generation
circuit
V
R2
-VR
VR
V
IN
GND
BF
S
11
(S
13
)
GND
VR = -V
R2
Fig. 4.12.5
Differential voltage measurement
(3) Resistance measurement
• Measurement terminal: AI2–AI4 and AI3–AI4
• Reference resistance: 1/2 of maximum resistance value of the
measured resistance (1 kΩ to 1 MΩ)
• Measured resistance: Thermistor, variable resistance, etc.
(maximum resistance value : minimum
resistance value = 4 : 1)
• Resistance for stabilization: It is unnecessary when the reference
resistance is 10 kΩ or less. (10 kΩ to 30 kΩ)