Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-80 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
A/D Converter4.12
Configuration of A/D
converter
The S1C62740 has a built-in dual slope type A/D converter. This
A/D converter has 5 analog input terminals and voltage, differen-
tial voltage between two terminals and resistance can be measured
by specifying combinations with those terminal functions using
software. The resolution and conversion time of the four types
indicated below can be set by programs. However, the integral
resistance is installed outside, so it is necessary to modify it ac-
cordingly.
Resolution (count) Conversion time (msec)
6,552 500.0
3,276 250.0
1,638 125.0
820 62.5
See Chapter 7, "ELECTRICAL CHARACTERISTICS", for the conver-
sion precision.
Figure 4.12.1 shows the configuration of the A/D converter.
GND
VSS/VSSA
CH
CL
VDD/VDDA
AIF
AI0
AI1
AI2
AI3
AI4
VR1
VR2
VRA
GND
VR
-VR
VIN
Middle electric potential
(GND) generation circuit
Reference voltage
generation circuit
VR1, VR2
generation
circuit
VR, -VR
generation
circuit
GND
Analog input
control circuit
+
–
Selector
+
–
+
–
CAZ CI
RI
BF
CO
INT
CMP
BUF
A/D converter
control circuit
OSC1 clock
32,768 Hz
Dual slope counter
Fig. 4.12.1
Configuration of A/D converter