Specifications

S1C62740 TECHNICAL HARDWARE EPSON I-79
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
(1) When using the serial interface in the master mode, the syn-
chronous clock uses the CPU system clock. Accordingly, do not
change the system clock (f
OSC1 ↔ fOSC3) while the serial inter-
face is operating.
(2) Perform data writing/reading to data registers SD0–SD7 only
while the serial interface is halted (i.e., the synchronous clock is
neither being input or output).
(3) As a trigger condition, it is required that data writing or reading
on data registers SD0–SD7 be performed prior to writing "1" to
SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.)
Supply trigger only once every time the serial interface is placed
in the RUN state. Moreover, when the synchronous clock SCLK
is external clock, start to input the external clock after the
trigger.
(4) Write the interrupt mask register (EISIO) only in the DI status
(interrupt flag = "0"). Writing during EI status (interrupt flag =
"1") will cause malfunction.
(5) Reading of interrupt factor flags is available at EI, but be careful
in the following cases.
If the interrupt mask register value corresponding to the inter-
rupt factor flags to be read is set to "1", an interrupt request will
be generated by the interrupt factor flags set timing, or an
interrupt request will not be generated.
Programming notes