Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-76 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Sets the pull up of SIN terminal and SCLK terminal (in the slave
mode).
When "1" is written: Pull up ON
When "0" is written: Pull up OFF
Reading: Valid
Sets the pull up resistor built into the SIN (P20) and SCLK (P22)
ports to ON or OFF. SCLK pull up is effective during the slave
mode.
At initial reset, this register is set to "0" and pull up goes OFF.
PUP2:
Pull up control register
(D7H•D2)
SCS0, SCS1:
Synchronous clock selection
(DBH•D0, D1)
Selects the synchronous clock for the serial interface (SCLK).
Table 4.11.3
Synchronous clock selection
SCS1 SCS0 Mode Synchronous clock
1 1 CLK
1 0 Master mode CLK/2
0 1 PTOVF
0 0 Slave mode External clock
CLK : CPU system clock
PTOVF: Programmable timer output clock (See Section 4.10.)
Synchronous clock (SCLK) is selected from among the above 4
types: 3 types of internal clock and external clock.
When using the serial interface in the master mode, CPU system
clock is used as the synchronous clock. Accordingly, when the
serial interface is operating, system clock switching (f
OSC1 ↔ fOSC3)
should not be performed.
Also, when PTOVF is used, it is necessary to generate a clock on
the programmable timer side prior to sending and receiving.
At initial reset, external clock is selected.
SDP:
Data input/output permutation
selection
(DBH•D2)
Selects the serial data input/output permutation.
When "1" is written: LSB first
When "0" is written: MSB first
Reading: Valid
Select whether the data input/output permutation will be MSB
first or LSB first.
At initial reset, this register is set to "0".