Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-75
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Table 4.11.2 list the serial interface control bits and their ad-
dresses.
Control of serial
interface
Table 4.11.2 Control bits of serial interface
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
C1H
ISIO
R
0
0
0
ISIO
–
–
–
0
Yes No
000
*2
*2
*2
*5
*5
*5
*4
C8H
EIPT
0
EIAD
EISIO
EIPT
0
0
0
Unused
Interrupt mask register (A/D converter)
Interrupt mask register (serial interface)
Interrupt mask register (programmable timer)
Enable
Enable
Enable
Mask
Mask
Mask
EISIOEIAD0
*2
*5
*7
R/W
Unused
Unused
Unused
Interrupt factor flag (serial interface)
R
DBH
SCS0
R/W
PFS
SDP
SCS1
SCS0
0
0
0
0
Serial I/F
LSB first
I/O port
MSB first
SCS1PFS
*6
DCH
SCTRG
0
0
SCRUN
SCTRG
–
–
0
–
Run
Trigger
Stop
–
SCRUN00
*2
*2
*2
*5
*5
*5
P2 port function selection
Serial data input/output permutation
Serial interface clock mode selection
0: slave, 1: PTOVF, 2: CLK/2, 3: CLK
R
Unused
Unused
Serial interface status
Serial interface clock trigger
SDP
DDH
SD0
SD3
SD2
SD1
SD0
–
–
–
–
SD1SD2SD3
R/W
DEH
SD4
SD7
SD6
SD5
SD4
–
–
–
–
SD5SD6SD7
R/W
W
*2
*2
*2
*2
*2
*2
*2
*2
Serial interface data (low-order 4 bits)
LSB
Serial interface data (high-order 4 bits)
MSB
D7H
PUP0
R/W
0
PUP2
PUP1
PUP0
–
0
0
0
Unused
Pull up control register 2 (P20–P23)
Pull up control register 1 (P10–P13)
Pull up control register 0 (P00–P03)
On
On
On
Off
Off
Off
PUP1PUP20
*2
*6
R
*5
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
PFS:
P2 port function selection
(DBH•D3)
Sets P20–P23 to the input/output port for the serial interface.
When "1" is written: Serial interface
When "0" is written: I/O port
Reading: Valid
P20, P21, P22 and P23 will function as SIN, SOUT, SCLK, SRDY,
respectively.
At initial reset, this register is set to "0".