Specifications

S1C62740 TECHNICAL HARDWARE EPSON I-73
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
When the input of the 8 bits data from SD0 to SD7 is com-
pleted, the interrupt factor flag ISIO is set to "1" and interrupt is
generated. Moreover, the interrupt can be masked by the
interrupt mask register EISIO. Note, however, that regardless of
the setting of the interrupt mask register, the interrupt factor
flag is set to "1" after input of the 8 bits data.
The data input in the shift register can be read from data
registers SD0–SD7 by software.
(3) Serial data input/output permutation
S1C62740 allows the input/output permutation of serial data
to be selected by register SDP (DBH•D2) as to either LSB first or
MSB first. The block diagram showing input/output permuta-
tion in case of LSB first and MSB first is provided in Figure
4.11.3.
Fig. 4.11.3
Serial data input/output
permutation
(4) SRDY signal
When the S1C62740 serial interface is used in the slave mode
(external clock mode), SRDY is used to indicate whether the
internal serial interface is available to transmit or receive data
for the master side (external) serial device. SRDY signal is
output from SRDY (P23) terminal.
SRDY signal becomes "0" (low) when the S1C62740 serial
interface becomes available to transmit or receive data; nor-
mally, it is at "1" (high).
SRDY signal changes from "1" to "0" immediately after "1" is
written to SCTRG and returns from "0" to "1" when "0" is input
to SCLK (P22) terminal (i.e., when the serial input/output
begins transmitting or receiving data). Moreover, when data is
read from or written to SD4–SD7, the SRDY signal returns to
"1".
SIN
SIN
Address [DEH]
Address [DDH] Address [DEH]
Address [DDH]
Output
latch
Output
latch
SOUT
SOUT
SD3 SD2 SD1 SD0
SD4 SD5 SD6 SD7
SD7 SD6 SD5 SD4
SD0 SD1 SD2 SD3
(In case of LSB first)
(In case of MSB first)