Specifications

I-72 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
The serial interface of S1C62740 can input/output data via the
internal 8 bits shift register. The shift register operates by synchro-
nizing with either the synchronous clock output from SCLK (P22)
terminal (master mode), or the synchronous clock input to SCLK
(P22) terminal (slave mode).
The serial interface generates interrupt on completion of the 8 bits
serial data input/output. Detection of serial data input/output is
done by the counting of the synchronous clock SCLK; the clock
completes input/output operation when 8 counts (equivalent to 8
cycles) have been made and then generates interrupt.
The serial data input/output procedure data is explained below:
(1) Serial data output procedure and interrupt
The S1C62740 serial interface is capable of outputting parallel
data as serial data, in units of 8 bits.
By setting the parallel data to 4 bits registers SD0–SD3 (DDH)
and SD4–SD7 (DEH) individually and writing "1" to SCTRG bit
(DCH•D0), it synchronizes with the synchronous clock and
serial data is output at the SOUT (P21) terminal. The synchro-
nous clock used here is as follows: in the master mode, internal
clock which is output to the SCLK (P22) terminal while in the
slave mode, external clock which is input from the SCLK (P22)
terminal. The serial output of the SOUT (P21) terminal changes
with the falling edge of the clock that is input or output from
the SCLK (P22) terminal.
When the output of the 8 bits data from SD0 to SD7 is com-
pleted, the interrupt factor flag ISIO (C1H•D0) is set to "1" and
interrupt is generated. Moreover, the interrupt can be masked
by the interrupt mask register EISIO (C8H•D1). Note, however,
that regardless of the setting of the interrupt mask register, the
interrupt factor flag is set to "1" after output of the 8 bits data.
(2) Serial data input procedure and interrupt
The S1C62740 serial interface is capable of inputting serial data
as parallel data, in units of 8 bits.
The serial data is input from the SIN (P20) terminal, synchro-
nizes with the synchronous clock, and is sequentially read in
the 8 bits shift register. As in the above item (1), the synchro-
nous clock used here is as follows: in the master mode, internal
clock which is output to the SCLK (P22) terminal while in the
slave mode, external clock which is input from the SCLK (P22)
terminal.
The serial data to the built-in shift register is read with the
rising edge of the SCLK signal. Moreover, the shift register is
sequentially shifted as the data is fetched.
Data input/output
and interrupt
function