Specifications

S1C62740 TECHNICAL HARDWARE EPSON I-71
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
The serial interface of the S1C62740 has two types of operation
mode: master mode and slave mode.
In the master mode, it uses an internal clock as synchronous clock
of the built-in shift register, generates this internal clock at the
SCLK (P22) terminal and controls the external (slave side) serial
device.
In the slave mode, the synchronous clock output from the external
(master side) serial device is input from the SCLK (P22) terminal
and uses it as the synchronous clock to the built-in shift register.
The master mode and slave mode are selected by writing data to
registers SCS1 and SCS0.
When the master mode is selected, a synchronous clock may be
selected from among 3 types as shown in Table 4.11.1.
Master mode and
slave mode of serial
interface
Table 4.11.1
Synchronous clock selection
SCS1 SCS0 Mode Synchronous clock
1 1 CLK
1 0 Master mode CLK/2
0 1 PTOVF
0 0 Slave mode External clock
CLK : CPU system clock
PTOVF: Programmable timer output clock (See Section 4.10.)
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of
the 8 bits serial data, is controlled as follows:
• At master mode, after output of 8 clocks from the SCLK (P22)
terminal, clock output is automatically suspended and SCLK
(P22) terminal is fixed at high level.
• At slave mode, after input of 8 clocks to the SCLK (P22) termi-
nal, subsequent clock inputs are masked.
Note: When using the serial interface in the master mode, CPU system clock is
used as the synchronous clock. Accordingly, when the serial interface is
operating, system clock switching (f
OSC1 ↔ fosc3) should not be per-
formed.
A sample basic serial input/output portion connection is shown in
Figure 4.11.2.
S1C62740
SCLK
SOUT
SIN
Input terminal
External
Serial device
CLK
SOUT
SIN
READY
S1C62740
SCLK
SOUT
SIN
R33(SRDY)
External
Serial device
CLK
SOUT
SIN
Input terminal
(a) Master mode (b) Slave mode
Fig. 4.11.2
Sample basic connection of serial
input/output section