Specifications

I-70 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Serial Interface (SIN, SOUT, SCLK, SRDY)4.11
Configuration of
serial interface
The S1C62740 has a synchronous clock type 8 bits serial interface
built-in.
The configuration of the serial interface is shown in Figure 4.11.1.
The CPU, via the 8 bits shift register, can read the serial input data
from the SIN terminal. Moreover, via the same 8 bits shift register,
it can convert parallel data to serial data and output it to the SOUT
terminal.
The synchronous clock for serial data input/output may be set by
selecting by software any one of 3 types of master mode (internal
clock mode: when the S1C62740 is to be the master for serial
input/output) and a type of slave mode (external clock mode: when
the S1C62740 is to be the slave for serial input/output).
Also, when the serial interface is used at slave mode, SRDY signal
which indicates whether or not the serial interface is available to
transmit or receive can be output to the SRDY terminal.
SD0–SD7
SIN
(P20)
SCLK
(P22)
SCS0 SCS1
Output
latch
EISIO
Serial interface
interrupt control circuit
ISIO
SOUT
(P21)
SRDY
(P23)
SCTRG
Serial interface
activating circuit
System clock
Serial clock
counter
Serial clock
selector
Serial clock
generator
Shift register (8 bits)
PTOVF
Fig. 4.11.1
Configuration of serial
interface
The input/output ports of the serial interface are common used
with the I/O ports P20–P23, and function of these ports can be
selected through the software.
P20–P23 terminals and serial input/output correspondence are as
follows:
P20 = SIN P21 = SOUT P22 = SCLK P23 = SRDY