Specifications

S1C62740 TECHNICAL HARDWARE EPSON I-67
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
PTD0, PTD1:
Dividing ratio selection
(EAH•D2, D3)
Selects the dividing ratio in the predivider for the input clock.
PTD1 PTD0 Dividing ratio
0 0 1/256
0 1 1/32
10 1/4
11 1/1
At initial reset, these registers are set to "0".
RD0–RD3, RD4–RD7:
Reload register
(EDH•EEH)
These are reload registers for setting the initial value of the timer.
Sets the low-order 4 bits of the 8 bits timer data to RD0–RD3, and
the high-order 4 bits to RD4–RD7.
The set timer data is loaded to the down-counter when the pro-
grammable timer is reset or when the content of the down-counter
is "00H".
When data of reload registers is set at "00H", the down-counter
becomes a 256-value counter.
At initial reset, these registers will be undefined.
PTRST:
Programmable timer reset
(E9H•D0)
This bit resets the programmable timer.
When "1" is written: Programmable timer reset
When "0" is written: No operation
Reading: Always "0"
By writing "1" on PTRST, the programmable timer is reset.
The contents set in RD0–RD7 are loaded into the down-counter.
When the programmable timer is reset in the RUN mode, it will re-
start counting immediately after loading and at STOP mode, the
load data is maintained.
Because this bit is only for writing, it is always "0" during reading.
PTRUN:
Programmable timer
RUN/STOP
(E9H•D1)
This register controls RUN/STOP of the programmable timer.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
By writing "1" on PTRUN, the programmable timer performs count-
ing operation. Writing "0" will make the programmable timer stop
counting.
Even if the programmable timer is stopped, the timer data at that
point is kept.
At initial reset, PTRUN is set to "0".
Table 4.10.5
Clock dividing ratio selection