Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-65
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
Interrupt function
The programmable timer generates interrupt after the down-count
from the initial setting is completed and the content of the down-
counter indicates 00H.
After interrupt generation, the programmable timer reloads the
initial count value into the down-counter and resumes counting.
Figure 4.10.4 shows the timing chart of the programmable timer.
Fig. 4.10.4 Timing chart of the programmable timer
When the down-counter values PT0–PT7 have become 00H the
interrupt factor flag IPT is set to "1" and an interrupt is generated.
The interrupt can be masked through the interrupt mask register
EIPT. However, regardless of the setting of the interrupt mask
register, the interrupt factor flag is set to "1" when the down-
counter equals 00H.
Note:
PTRST
PTRUN
Count clock
D3
D2
D1
D0
D3
D2
D1
D0
Timer data
high-order
address
(ECH)
Timer data
low-order
address
(EBH)
PTOVF
Interrupt request Interrupt request Interrupt request
• When "A6H" is set into the reload register.
• The count clock is output from the predivider.