Specifications

I-64 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
(2) Data reload
The reload register (8 bits) for the initial value setting of the
down counter is built into the programmable timer. The data set
into the reload register is loaded into the down counter in the
following instances and the count down is done from that value.
1. When the programmable timer has been reset by software
2. When the count down advances and the down counter
becomes 00H
(3) Data reading
The low-order 4 bits of the down counter data is allocated to the
address EBH and the high-order 4 bits are allocated to ECH and
they can respectively be read.
At the time of this reading as well, the high-order data hold
function operates the same as the clock timer. Refer to Section
4.8, "Clock Timer" for details of the hold function.
(4) PTOVF signal
The programmable timer generates a PTOVF signal by inverting
the level each time the down counter becomes 00H.
PTOVF
Down counter = 00H
Fig. 4.10.3
PTOVF signal
The cycles (frequency) for this signal can be set according to the
input clock, the dividing ratio and initial value that has been set
for the reload register. The frequency of the output clock is
indicated by the following expression.
fout = fin × dv / (RD × 2)
fout: PTOVF frequency
fin: Input clock frequency
dv: Dividing ratio (1/256, 1/32, 1/4, 1/1)
RD: Reload data (1 to 256 (0))
This PTOVF signal is input into the serial interface and can be
used as the transfer clock. In addition, it can also be output
externally through the output port R01.