Specifications

S1C62740 TECHNICAL HARDWARE EPSON I-63
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
In case such as when counting by a key input, this causes it to
eliminate noise of 2 msec or less such as chattering and to
accept signals of 6 msec or more. (Acceptance of signals within
the range from 2 msec to 6 msec is uncertain.) The K10 input
(direct) is bypassed by this noise reject circuit. When it inputs a
clock of 6 msec or less, you should select direct.
f
OSC1 and fOSC3 are the respective output clocks of the OSC1
and OSC3 oscillation circuit.
When using f
OSC3, you must turn ON the OSC3 oscillation
circuit in advance. If the OSC3 oscillation circuit is ON, count-
ing can be done by f
OSC3, even when the CPU clock is fOSC1.
(2) Clock dividing ratio selection
For the programmable timer, the predivider that contains the
down counter is set up after the selector for the above men-
tioned clock source. The input clock dividing ratio can be
selected from four types. As shown in Table 4.10.2, this selec-
tion can be done by registers PTD0 and PTD1.
Run/Stop of the programmable timer can be controlled by
register PTRUN.
When initiating programmable timer count, perform program-
ming by the following steps:
1. Set the initial data to RD0–RD7.
2. Reset the programmable timer by writing "1" to PTRST.
3. Start the down-count by writing "1" to PTRUN.
Table 4.10.2
Clock dividing ratio selection
Operation of
programmable timer
(1) Down-count
The 8-bit down counter counts down the divided input clock
explained in the foregoing clause as the clock.
In case of K10 input, the down count timing becomes the falling
edge of the clock and in f
OSC1 and fOSC3 it becomes the rising
edge.
PTD1 PTD0 Dividing ratio
0 0 1/256
0 1 1/32
10 1/4
11 1/1
Fig. 4.10.2
Timing of down-counts
(predivider = 1/1)
K10 input
f
OSC1
fOSC3
Down count