Specifications

I-62 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
Programmable Timer4.10
Configuration of
programmable timer
S1C62740 has a programmable timer which is configured with an
8 bits pre-settable down counter.
Aside from the count by the built-in clock (f
OSC1/fOSC3), this
programmable timer also possesses an event counter function that
performs counting by making the signal input from the input port
K10 the clock.
The initial value of count data can be set by software to the reload
register; at the point where the down-counter value is "0", the
programmable timer reloads the initial value and continues to
down-count.
In addition, the clock created by the underflow of the down counter
can be output to the serial interface and to the output port R01.
Figure 4.10.1 shows the configuration of the programmable timer.
Fig. 4.10.1
Configuration of
the programmable
timer
(1) Clock source selection
The counter clock source can be selected among four types
shown in Table 4.10.1 by registers PTC0 and PTC1.
Input clock and pre-
divider
Table 4.10.1
Clock source selection
PTC1 PTC0 Clock source
0 0 K10 input (with noise rejector)
0 1 K10 input (direct)
10f
OSC1 (32 kHz)
11f
OSC3 (1 MHz)
The K10 input is an external input when used as an event
counter and when K10 input (with noise rejecter) has been
selected it passes through the noise reject circuit of the 256 Hz
sampling.
1/256, 1/32,
1/4, 1/1
K10
Selector
Predivider
OSC3
oscillation
circuit
Noise
rejecter
Programmable timer reset signal
Programmable timer RUN/STOP signal
Interrupt
control
Reload register
8-bit down counter
Data bus
Interrupt
request
OSC1
oscillation
circuit
PTOVF gen-
eration circuit
To R01 and
serial interface