Specifications

I-60 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
EISW0, EISW1:
Interrupt mask register
(CBH•D0, D1)
These registers are used to select whether to mask the stopwatch
timer interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers (EISW0, EISW1) are used to sepa-
rately select whether to mask the 10 Hz and 1 Hz interrupts.
Writing to the interrupt mask registers can be done only in the DI
status (interrupt flag = "0").
At initial reset, these registers are both set to "0".
ISW0, ISW1:
Interrupt factor flag
(C5H•D0, D1)
These flags indicate the status of the stopwatch timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags (ISW0, ISW1) correspond to the 10 Hz
and 1 Hz interrupts respectively. With these flags, the software can
judge whether a stopwatch timer interrupt has occurred. However,
regardless of the interrupt mask register setting, these flags are set
to "1" by the counter overflow.
These flags are reset when read out by the software.
Reading of interrupt factor flags is available at EI, but be careful in
the following cases.
If the interrupt mask register value corresponding to the interrupt
factor flags to be read is set to "1", an interrupt request will be
generated by the interrupt factor flags set timing, or an interrupt
request will not be generated. Be very careful when interrupt factor
flags are in the same address.
At initial reset, these flags are set to "0".
SWRST:
Stopwatch timer reset
(E6H•D0)
This bit resets the stopwatch timer.
When "1" is written: Stopwatch timer reset
When "0" is written: No operation
Reading: Always "0"
The stopwatch timer is reset when "1" is written to SWRST. When
the stopwatch timer is reset in the RUN status, operation restarts
immediately. Also, in the STOP status the reset data is maintained.
This bit is write-only, and is always "0" at reading.