Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-52 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
The clock timer can cause interrupts at the falling edge of 32 Hz, 8
Hz, 2 Hz and 1 Hz signals. Software can set whether to mask any of
these frequencies.
Figure 4.8.2 is the timing chart of the clock timer.
Interrupt function
Clock timer timing chart
FrequencyRegisterAddress
E4H
D3
D0
D1
D2
4 Hz
2 Hz
32 Hz interrupt request
8 Hz interrupt request
1 Hz interrupt request
E3H
2 Hz interrupt request
D3 1 Hz
D0
D1
D2
128 Hz
16 Hz
8 Hz
32 Hz
64 Hz
Fig. 4.8.2 Timing chart of clock timer
As shown in Figure 4.8.2, interrupt is generated at the falling edge
of the frequencies (32 Hz, 8 Hz, 2 Hz, 1 Hz). At this time, the
corresponding interrupt factor flag (IT32, IT8, IT2, IT1) is set to "1".
Selection of whether to mask the separate interrupts can be made
with the interrupt mask registers (EIT32, EIT8, EIT2, EIT1). How-
ever, regardless of the interrupt mask register setting, the interrupt
factor flag is set to "1" at the falling edge of the corresponding
signal.
Note: • Reading of interrupt factor flags is available at EI, but be careful in the
following cases.
If the interrupt mask register value corresponding to the interrupt factor
flags to be read is set to "1", an interrupt request will be generated by
the interrupt factor flags set timing, or an interrupt request will not be
generated. Be very careful when interrupt factor flags are in the same
address.
• Write the interrupt mask register only in the DI status (interrupt flag =
"0"). Writing during EI status (interrupt flag = "1") will cause malfunction.