Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-50 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
LDTY1, LDTY0:
LCD drive duty selection
(EFH•D3, D2)
Sets the LCD drive duty as shown in Table 4.7.3
Table 4.7.3
LCD drive duty setting
At initial reset, these registers are set to "0".
Display memory
(80H–9FH)
The LCD segments are lit or turned off depending on this data.
When "1" is written: Lit
When "0" is written: Not lit
Reading: Invalid
By writing data into the display memory allocated to the LCD
segment (on the panel), the segment can be lit or put out.
At initial reset, the contents of the display memory for COM0 is set
to "1", and COM1–COM3 are undefined. Accordingly, when DC
output is selected, the output level at initial reset goes high (V
DD).
Programming notes
(1) The contents of the display memory are undefined until the area
is initialized (through, for instance, memory clear processing by
the CPU). Initialize the display memory by executing initial
processing.
(2) Since the display memory area is write-only, display data
cannot be rewritten by arithmetic operations (such as AND, OR,
ADD, SUB).
Terminals used Maximum number
in common of segments
0 0 1/4 COM0–COM3 128 (32 × 4) fOSC1/1,024 (32 Hz)
0 1 1/3 COM0–COM2 96 (32 × 3) f
OSC1/768 (42.7 Hz)
1 0 1/2 COM0, COM1 64 (32 × 2) f
OSC1/1,024 (32 Hz)
1 1 1/1 COM0 32 (32 × 1) f
OSC1/1,024 (32 Hz)
* In case of f
OSC1 = 32,768 Hz
LDTY1 LDTY0 Duty Frame frequency
*