Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-49
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
(2) Output specification
➀ The segment terminals (SEG0–SEG31) are selected with the
mask option in pairs for either segment signal output or DC
output (V
DD and VSS binary output).
When DC output is selected, the data corresponding to
COM0 of each segment terminal is output.
➁ When DC output is selected, either complementary output or
Nch open drain output can be selected for each terminal
with the mask option.
Note: The terminal pairs are the combination of SEG2
×
n and SEG2
×
n + 1
(where n is an integer from 0 to 15).
Control of LCD driver
Table 4.7.2 shows the LCD driver's control bits and their ad-
dresses. Figure 4.7.6 shows the display memory map.
Table 4.7.2 LCD driver control bits
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Address
Page High
Low
0123456789ABCDEF
8
9
Display memory (32 words x 4 bits) W
0–3
Fig. 4.7.6 Display memory map
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
*7
EFH
LCDON
R/W
LDTY1
LDTY0
0
LCDON
0
0
–
0
On Off
0
R
LDTY0LDTY1
*5
LCD drive duty selection
0: 1/4, 1: 1/3, 2: 1/2, 3: 1/1
Unused
LCD display control (LCD display all off)
*2
R/W
LCDON:
Display control
(EFH•D0)
Controls the LCD display
When "1" is written: Display ON
When "0" is written: Display OFF
Reading: Valid
By writing "1" to LCDON, the LCD display goes ON, and goes OFF
when "0" is written. The LCD display OFF setting does not affect
the contents of the display memory.
At initial reset, this register is set to "0".