Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-38 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
Controls the FOUT (clock) output.
When "1" is written: High level (DC) output
When "0" is written: Clock output
Reading: Valid
FOUT output can be controlled by writing data to R00.
At initial reset, this register is set to "1".
R00
(when FOUT is selected):
Special output port data
(D4H•D0)
FOFQ0, FOFQ1:
FOUT frequency selection
register
(E1H•D0, D1)
Selects the FOUT frequency.
FOFQ1 FOFQ0 Clock frequency (Hz)
11 fOSC3
10 fOSC1
0 1 4,096
0 0 512
At initial reset, these registers are set to "0".
Table 4.5.4
FOUT clock frequency
R01
(when PTOVF is selected):
Special output port data
(D4H•D0)
Controls the PTOVF (clock) output.
When "1" is written: High level (DC) output
When "0" is written: Clock output
Reading: Valid
PTOVF output can be controlled by writing data to R01.
Refer to Section 4.10, "Programmable Timer" for details of PTOVF.
At initial reset, this register is set to "1".
Programming note
When BZ, BZ, FOUT and PTOVF are selected, a hazard may be
observed in the output waveform when the data of the output
register changes.