Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-34 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
Fig. 4.5.2
Structure of the
output ports R00–R03
BZ and BZ are the buzzer signal output for driving the piezo-
electric buzzer.
By setting the register BZR02 to "1", R02 is set to BZ (buzzer
signal) output port and by setting the register BZR03 to "1", R03 is
set to BZ (buzzer inverted signal) output port. When BZR02 and
BZR03 are set to "0", R02 and R03 become the regular DC output
ports.
When the buzzer output and the buzzer inverted output are se-
lected, ON/OFF of the buzzer outputs can be controlled by the R02
and R03 registers, respectively.
The buzzer frequency may be selected as 2 kHz or 4 kHz by setting
of the BZFQ register.
• BZ and BZ
(R02 and R03)
Note: The BZ and BZ output signals could generate hazards during ON/OFF
switching.
Figure 4.5.3 shows the output waveform of BZ and BZ.
Fig. 4.5.3
Output waveform of BZ and BZ
R02 register
BZ output
001
R03 register
BZ output
001
BZ
Data bus
R03
(BZ)
Register
BZR03
Register
R03
R02
(BZ)
Register
BZR02
Register
R02
PTOVF
R01
(PTOVF)
Register
PTR01
Register
R01
FOUT
R00
(FOUT)
Register
FOR00
Register
R00