Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-31
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
DFK00–DFK03, DFK10:
Input comparison registers
(D2H, D3H•D0)
Interrupt conditions for terminals K00–K03 and K10 can be set
with these registers.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading: Valid
The interrupt conditions can be set for the rising or falling edge of
input for each of the five bits (K00–K03 and K10), through the
input comparison registers (DFK00–DFK03 and DFK10).
For DFK00–DFK03, a comparison is done only with the ports that
are enabled by the interrupt among K00–K03 by means of the SIK
register.
At initial reset, these registers are set to "0".
SIK00–SIK03:
Interrupt selection register
(CAH)
Selects the port to be used for the K00–K03 input interrupt.
When "1" is written: Enable
When "0" is written: Disable
Reading: Valid
Enables the interrupt for the input ports (K00–K03) for which "1"
has been written into the interrupt selection register (SIK00–
SIK03). The input port set for "0" does not affect the interrupt
generation condition.
At initial reset, these registers are set to "0".
EIK0, EIK1:
Interrupt mask registers
(C9H•D0, D1)
Masking the interrupt of the input port can be selected with these
registers.
When "1" is written: Enable
When "0" is written: Mask
Reading: Valid
With these registers, masking of the input port can be selected for
each of the two systems (K00–K03, K10).
Writing to the interrupt mask registers can be done only in the DI
status (interrupt flag = "0").
At initial reset, these registers are all set to "0".
IK0, IK1:
Interrupt factor flags
(C3H•D0, C2H•D0)
These flags indicate the occurrence of input interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags IK0 and IK1 are associated with K00–K03
and K10, respectively. From the status of these flags, the software
can decide whether an input interrupt has occurred. However,
these flags are set to "1" when the interrupt conditions are estab-
lished even if the interrupts have been masked.