Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-28 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Interrupt selection register Input comparison register
SIK03 SIK02 SIK01 SIK00 DFK03DFK02 DFK01 DFK00
1110 1010
With the above setting, the interrupt of K00–K03 is generated under the
following condition:
Input port
(1) K03 K02 K01 K00
1 0 1 0 (Initial value)
↓
(2) K03 K02 K01 K00
1011
↓
(3) K03 K02 K01 K00
0011 → Interrupt generation
↓
(4) K03 K02 K01 K00
0111
Because K00 interrupt is set to disable,
interrupt will be generated when no
matching occurs between the contents of
the 3 bits K01–K03 and the 3 bits input
comparison register DFK01–DFK03.
Fig. 4.4.3
Example of interrupt of K00–K03
K00 interrupt is disabled by the interrupt selection register (SIK00),
so that an interrupt does not occur at (2). At (3), K03 changes to
"0"; the data of the terminal that is interrupt enabled no longer
matches the data of the input comparison register, so that inter-
rupt occurs. As already explained, the condition for the interrupt to
occur is the change in the port data and contents of the input
comparison register from matching to no matching. Hence, in (4),
when the no matching status changes to another no matching
status, an interrupt does not occur. Further, terminals that have
been masked for interrupt do not affect the conditions for interrupt
generation.