Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
S1C62740 TECHNICAL HARDWARE EPSON I-25
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
Clock frequency
and instruction
execution time
Table 4.3.2 shows the instruction execution time according to each
frequency of the system clock.
Instruction execution time (µsec)
5-clock instruction 7-clock instruction
12-clock instruction
OSC1: 32.768 kHz 152.6 213.6 366.2
OSC3: 1 MHz 5.0 7.0 12.0
Clock frequency
Table 4.3.2
Clock frequency and instruction
execution time
Programming notes
(1) It takes at least 5 msec from the time the OSC3 oscillation
circuit goes ON until the oscillation stabilizes. Consequently,
when switching the CPU operation clock from OSC1 to OSC3,
do this after a minimum of 5 msec have elapsed since the OSC3
oscillation went ON.
Further, the oscillation stabilization time varies depending on
the external oscillator characteristics and conditions of use, so
allow ample margin when setting the wait time.
(2) When switching the clock form OSC3 to OSC1, use a separate
instruction for switching the OSC3 oscillation OFF. An error in
the CPU operation can result if this processing is performed at
the same time by the one instruction.
(3) When shifting to the SLEEP status, the CPU clock must be set
to OSC1 and the OSC3 oscillation circuit must be OFF.