Specifications
Table Of Contents
- Technical Hardware
- 1 OVERVIEW
- 2 POWER SUPPLY AND INITIAL RESET
- 3 CPU, ROM, RAM
- 4 PERIPHERAL CIRCUITS AND OPERATION
- 4.1 Memory Map
- 4.2 Resetting Watchdog Timer
- 4.3 Oscillation Circuit
- 4.4 Input Ports (K00–K03, K10)
- 4.5 Output Ports (R00–R03)
- 4.6 I/O Ports (P00–P03, P10–P13, P20–P23)
- 4.7 LCD Driver (COM0–COM3, SEG0–SEG31)
- 4.8 Clock Timer
- 4.9 Stopwatch Timer
- 4.10 Programmable Timer
- 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)
- 4.12 A/D Converter
- 4.13 General-purpose Operation Amplifier (AMP)
- 4.14 SVD (Supply Voltage Detection) Circuit
- 4.15 Interrupt and HALT/SLEEP
- 5 SUMMARY OF NOTES
- 6 DIAGRAM OF BASIC EXTERNAL CONNECTIONS
- 7 CHARACTERISTICS
- 8 PACKAGE
- 9 PAD LAYOUT
- Technical Software
- 1 INTRODUCTION
- 2 BLOCK DIAGRAM
- 3 PROGRAM MEMORY (ROM)
- 4 DATA MEMORY
- 5 INITIAL RESET
- 6 PERIPHERAL CIRCUITS
- 6.1 Watchdog Timer
- 6.2 OSC3
- 6.3 Input Ports (K00–K03 and K10)
- 6.4 Output Ports (R00–R03)
- 6.5 I/O Ports (P00–P03, P10–P13 and P20–P23)
- 6.6 LCD Driver
- 6.7 Clock Timer
- 6.8 Stopwatch Timer
- 6.9 Programmable Timer
- 6.10 Serial Interface Circuit
- 6.11 Amplifier
- 6.12 SVD (Supply Voltage Detection) Circuit
- 6.13 A/D Converter
- 6.14 Sleep
- 6.15 Interrupt
- 7 SUMMARY OF NOTES
- APPENDIX
I-24 EPSON S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
Control of oscillation
circuit
Table 4.3.1 lists the control bits and their addresses for the oscilla-
tion circuit.
Table 4.3.1 Control bits of oscillation circuit
*1 Initial value at the time of initial reset *5 Constantly "0" when being read
*2 Not set in the circuit *6 Refer to main manual
*3 Undefined *7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
OSCC:
OSC3 oscillation control
(DFH•D0)
Controls oscillation ON/OFF for the OSC3 oscillation circuit.
When "1" is written: The OSC3 oscillation ON
When "0" is written: The OSC3 oscillation OFF
Reading: Valid
When it is necessary to operate the CPU at high speed, set OSCC to
"1". At other times, set it to "0" to lessen the current consumption.
When "Not Use" is selected for the mask option of the OSC3 oscilla-
tion circuit, keep OSCC set to "0".
At initial reset, OSCC is set to "0".
CLKCHG:
The CPU's clock switch
(DFH•D1)
The CPU's operation clock is selected with this register.
When "1" is written: OSC3 clock is selected
When "0" is written: OSC1 clock is selected
Reading: Valid
When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1,
set CLKCHG to "0".
When "Not Use" is selected for the mask option of the OSC3 oscilla-
tion circuit, keep CLKCHG set to "0".
At initial reset, CLKCHG is set to "0".
Address
Comment
Register
D3 D2 D1 D0 Name Init 1 0
*1
*7
DFH
OSCC
0
0
CLKCHG
OSCC
–
–
0
0
OSC3
On
OSC1
Off
CLKCHG00
*5
*5
R/W
Unused
Unused
CPU system clock switch
OSC3 oscillation On/Off
*2
*2
R